Lines Matching refs:gp
117 static u16 __sungem_phy_read(struct gem *gp, int phy_addr, int reg)
127 writel(cmd, gp->regs + MIF_FRAME);
130 cmd = readl(gp->regs + MIF_FRAME);
145 struct gem *gp = netdev_priv(dev);
146 return __sungem_phy_read(gp, mii_id, reg);
149 static inline u16 sungem_phy_read(struct gem *gp, int reg)
151 return __sungem_phy_read(gp, gp->mii_phy_addr, reg);
154 static void __sungem_phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
165 writel(cmd, gp->regs + MIF_FRAME);
168 cmd = readl(gp->regs + MIF_FRAME);
178 struct gem *gp = netdev_priv(dev);
179 __sungem_phy_write(gp, mii_id, reg, val & 0xffff);
182 static inline void sungem_phy_write(struct gem *gp, int reg, u16 val)
184 __sungem_phy_write(gp, gp->mii_phy_addr, reg, val);
187 static inline void gem_enable_ints(struct gem *gp)
190 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
193 static inline void gem_disable_ints(struct gem *gp)
196 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
197 (void)readl(gp->regs + GREG_IMASK); /* write posting */
200 static void gem_get_cell(struct gem *gp)
202 BUG_ON(gp->cell_enabled < 0);
203 gp->cell_enabled++;
205 if (gp->cell_enabled == 1) {
207 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
214 static void gem_put_cell(struct gem *gp)
216 BUG_ON(gp->cell_enabled <= 0);
217 gp->cell_enabled--;
219 if (gp->cell_enabled == 0) {
221 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
227 static inline void gem_netif_stop(struct gem *gp)
229 netif_trans_update(gp->dev); /* prevent tx timeout */
230 napi_disable(&gp->napi);
231 netif_tx_disable(gp->dev);
234 static inline void gem_netif_start(struct gem *gp)
240 netif_wake_queue(gp->dev);
241 napi_enable(&gp->napi);
244 static void gem_schedule_reset(struct gem *gp)
246 gp->reset_task_pending = 1;
247 schedule_work(&gp->reset_task);
250 static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
252 if (netif_msg_intr(gp))
253 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
256 static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
258 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
261 if (netif_msg_intr(gp))
263 gp->dev->name, pcs_istat);
274 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
277 (readl(gp->regs + PCS_MIISTAT) &
292 netif_carrier_on(gp->dev);
295 netif_carrier_off(gp->dev);
299 if (!timer_pending(&gp->link_timer))
306 static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
308 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
310 if (netif_msg_intr(gp))
312 gp->dev->name, txmac_stat);
359 static int gem_rxmac_reset(struct gem *gp)
361 struct net_device *dev = gp->dev;
367 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
369 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
378 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
379 gp->regs + MAC_RXCFG);
381 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
391 writel(0, gp->regs + RXDMA_CFG);
393 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
405 writel(gp->swrst_base | GREG_SWRST_RXRST,
406 gp->regs + GREG_SWRST);
408 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
419 struct gem_rxd *rxd = &gp->init_block->rxd[i];
421 if (gp->rx_skbs[i] == NULL) {
426 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
428 gp->rx_new = gp->rx_old = 0;
431 desc_dma = (u64) gp->gblock_dvma;
433 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
434 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
435 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
438 writel(val, gp->regs + RXDMA_CFG);
439 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
442 gp->regs + RXDMA_BLANK);
446 gp->regs + RXDMA_BLANK);
447 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
448 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
449 writel(val, gp->regs + RXDMA_PTHRESH);
450 val = readl(gp->regs + RXDMA_CFG);
451 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
452 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
453 val = readl(gp->regs + MAC_RXCFG);
454 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
459 static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
461 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
464 if (netif_msg_intr(gp))
466 gp->dev->name, rxmac_stat);
469 u32 smac = readl(gp->regs + MAC_SMACHINE);
475 ret = gem_rxmac_reset(gp);
493 static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
495 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
497 if (netif_msg_intr(gp))
499 gp->dev->name, mac_cstat);
506 gp->pause_entered++;
509 gp->pause_last_time_recvd = (mac_cstat >> 16);
514 static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
516 u32 mif_status = readl(gp->regs + MIF_STATUS);
522 gem_handle_mif_event(gp, reg_val, changed_bits);
527 static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
529 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
531 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
532 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
553 pci_errs = pci_status_get_and_clear_errors(gp->pdev);
578 static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
582 if (netif_msg_rx_err(gp))
584 gp->dev->name);
590 if (netif_msg_rx_err(gp))
592 gp->dev->name);
599 if (gem_pcs_interrupt(dev, gp, gem_status))
604 if (gem_txmac_interrupt(dev, gp, gem_status))
609 if (gem_rxmac_interrupt(dev, gp, gem_status))
614 if (gem_mac_interrupt(dev, gp, gem_status))
619 if (gem_mif_interrupt(dev, gp, gem_status))
624 if (gem_pci_interrupt(dev, gp, gem_status))
631 static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
635 entry = gp->tx_old;
644 if (netif_msg_tx_done(gp))
646 gp->dev->name, entry);
647 skb = gp->tx_skbs[entry];
664 gp->tx_skbs[entry] = NULL;
668 txd = &gp->init_block->txd[entry];
673 dma_unmap_page(&gp->pdev->dev, dma_addr, dma_len,
681 gp->tx_old = entry;
691 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))) {
696 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
702 static __inline__ void gem_post_rxds(struct gem *gp, int limit)
706 cluster_start = curr = (gp->rx_new & ~(4 - 1));
714 &gp->init_block->rxd[cluster_start];
716 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
728 writel(kick, gp->regs + RXDMA_KICK);
746 static int gem_rx(struct gem *gp, int work_to_do)
748 struct net_device *dev = gp->dev;
752 if (netif_msg_rx_status(gp))
754 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
756 entry = gp->rx_new;
758 done = readl(gp->regs + RXDMA_DONE);
760 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
780 done = readl(gp->regs + RXDMA_DONE);
788 skb = gp->rx_skbs[entry];
808 new_skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
813 dma_unmap_page(&gp->pdev->dev, dma_addr,
814 RX_BUF_ALLOC_SIZE(gp), DMA_FROM_DEVICE);
815 gp->rx_skbs[entry] = new_skb;
816 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
817 rxd->buffer = cpu_to_le64(dma_map_page(&gp->pdev->dev,
820 RX_BUF_ALLOC_SIZE(gp),
836 dma_sync_single_for_cpu(&gp->pdev->dev, dma_addr, len,
839 dma_sync_single_for_device(&gp->pdev->dev, dma_addr,
853 skb->protocol = eth_type_trans(skb, gp->dev);
855 napi_gro_receive(&gp->napi, skb);
864 gem_post_rxds(gp, entry);
866 gp->rx_new = entry;
869 netdev_info(gp->dev, "Memory squeeze, deferring packet\n");
876 struct gem *gp = container_of(napi, struct gem, napi);
877 struct net_device *dev = gp->dev;
883 if (unlikely(gp->status & GREG_STAT_ABNORMAL)) {
893 reset = gem_abnormal_irq(dev, gp, gp->status);
896 gem_schedule_reset(gp);
903 gem_tx(dev, gp, gp->status);
910 work_done += gem_rx(gp, budget - work_done);
915 gp->status = readl(gp->regs + GREG_STAT);
916 } while (gp->status & GREG_STAT_NAPI);
919 gem_enable_ints(gp);
927 struct gem *gp = netdev_priv(dev);
929 if (napi_schedule_prep(&gp->napi)) {
930 u32 gem_status = readl(gp->regs + GREG_STAT);
933 napi_enable(&gp->napi);
936 if (netif_msg_intr(gp))
938 gp->dev->name, gem_status);
940 gp->status = gem_status;
941 gem_disable_ints(gp);
942 __napi_schedule(&gp->napi);
955 struct gem *gp = netdev_priv(dev);
957 disable_irq(gp->pdev->irq);
958 gem_interrupt(gp->pdev->irq, dev);
959 enable_irq(gp->pdev->irq);
965 struct gem *gp = netdev_priv(dev);
970 readl(gp->regs + TXDMA_CFG),
971 readl(gp->regs + MAC_TXSTAT),
972 readl(gp->regs + MAC_TXCFG));
974 readl(gp->regs + RXDMA_CFG),
975 readl(gp->regs + MAC_RXSTAT),
976 readl(gp->regs + MAC_RXCFG));
978 gem_schedule_reset(gp);
993 struct gem *gp = netdev_priv(dev);
1007 if (unlikely(TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1))) {
1016 entry = gp->tx_new;
1017 gp->tx_skbs[entry] = skb;
1020 struct gem_txd *txd = &gp->init_block->txd[entry];
1025 mapping = dma_map_page(&gp->pdev->dev,
1051 first_mapping = dma_map_page(&gp->pdev->dev,
1064 mapping = skb_frag_dma_map(&gp->pdev->dev, this_frag,
1070 txd = &gp->init_block->txd[entry];
1080 txd = &gp->init_block->txd[first_entry];
1087 gp->tx_new = entry;
1088 if (unlikely(TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))) {
1097 if (TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
1100 if (netif_msg_tx_queued(gp))
1104 writel(gp->tx_new, gp->regs + TXDMA_KICK);
1109 static void gem_pcs_reset(struct gem *gp)
1115 val = readl(gp->regs + PCS_MIICTRL);
1117 writel(val, gp->regs + PCS_MIICTRL);
1120 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1126 netdev_warn(gp->dev, "PCS reset bit would not clear\n");
1129 static void gem_pcs_reinit_adv(struct gem *gp)
1136 val = readl(gp->regs + PCS_CFG);
1138 writel(val, gp->regs + PCS_CFG);
1143 val = readl(gp->regs + PCS_MIIADV);
1146 writel(val, gp->regs + PCS_MIIADV);
1151 val = readl(gp->regs + PCS_MIICTRL);
1154 writel(val, gp->regs + PCS_MIICTRL);
1156 val = readl(gp->regs + PCS_CFG);
1158 writel(val, gp->regs + PCS_CFG);
1164 val = readl(gp->regs + PCS_SCTRL);
1165 if (gp->phy_type == phy_serialink)
1169 writel(val, gp->regs + PCS_SCTRL);
1174 static void gem_reset(struct gem *gp)
1180 writel(0xffffffff, gp->regs + GREG_IMASK);
1183 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1184 gp->regs + GREG_SWRST);
1190 val = readl(gp->regs + GREG_SWRST);
1196 netdev_err(gp->dev, "SW reset is ghetto\n");
1198 if (gp->phy_type == phy_serialink || gp->phy_type == phy_serdes)
1199 gem_pcs_reinit_adv(gp);
1202 static void gem_start_dma(struct gem *gp)
1207 val = readl(gp->regs + TXDMA_CFG);
1208 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1209 val = readl(gp->regs + RXDMA_CFG);
1210 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1211 val = readl(gp->regs + MAC_TXCFG);
1212 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1213 val = readl(gp->regs + MAC_RXCFG);
1214 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1216 (void) readl(gp->regs + MAC_RXCFG);
1219 gem_enable_ints(gp);
1221 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1226 static void gem_stop_dma(struct gem *gp)
1231 val = readl(gp->regs + TXDMA_CFG);
1232 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1233 val = readl(gp->regs + RXDMA_CFG);
1234 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1235 val = readl(gp->regs + MAC_TXCFG);
1236 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1237 val = readl(gp->regs + MAC_RXCFG);
1238 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1240 (void) readl(gp->regs + MAC_RXCFG);
1247 static void gem_begin_auto_negotiation(struct gem *gp,
1260 if (gp->phy_type != phy_mii_mdio0 &&
1261 gp->phy_type != phy_mii_mdio1)
1265 if (found_mii_phy(gp))
1266 features = gp->phy_mii.def->features;
1271 if (gp->phy_mii.advertising != 0)
1272 advertise &= gp->phy_mii.advertising;
1274 autoneg = gp->want_autoneg;
1275 speed = gp->phy_mii.speed;
1276 duplex = gp->phy_mii.duplex;
1311 if (!netif_device_present(gp->dev)) {
1312 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1313 gp->phy_mii.speed = speed;
1314 gp->phy_mii.duplex = duplex;
1319 gp->want_autoneg = autoneg;
1321 if (found_mii_phy(gp))
1322 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1323 gp->lstate = link_aneg;
1325 if (found_mii_phy(gp))
1326 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1327 gp->lstate = link_force_ok;
1331 gp->timer_ticks = 0;
1332 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1338 static int gem_set_link_modes(struct gem *gp)
1340 struct netdev_queue *txq = netdev_get_tx_queue(gp->dev, 0);
1348 if (found_mii_phy(gp)) {
1349 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1351 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1352 speed = gp->phy_mii.speed;
1353 pause = gp->phy_mii.pause;
1354 } else if (gp->phy_type == phy_serialink ||
1355 gp->phy_type == phy_serdes) {
1356 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1358 if ((pcs_lpa & PCS_MIIADV_FD) || gp->phy_type == phy_serdes)
1363 netif_info(gp, link, gp->dev, "Link is up at %d Mbps, %s-duplex\n",
1378 writel(val, gp->regs + MAC_TXCFG);
1382 (gp->phy_type == phy_mii_mdio0 ||
1383 gp->phy_type == phy_mii_mdio1)) {
1392 writel(val, gp->regs + MAC_XIFCFG);
1398 val = readl(gp->regs + MAC_TXCFG);
1399 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1401 val = readl(gp->regs + MAC_RXCFG);
1402 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1404 val = readl(gp->regs + MAC_TXCFG);
1405 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1407 val = readl(gp->regs + MAC_RXCFG);
1408 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1411 if (gp->phy_type == phy_serialink ||
1412 gp->phy_type == phy_serdes) {
1413 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1420 writel(512, gp->regs + MAC_STIME);
1422 writel(64, gp->regs + MAC_STIME);
1423 val = readl(gp->regs + MAC_MCCFG);
1428 writel(val, gp->regs + MAC_MCCFG);
1430 gem_start_dma(gp);
1434 if (netif_msg_link(gp)) {
1436 netdev_info(gp->dev,
1438 gp->rx_fifo_sz,
1439 gp->rx_pause_off,
1440 gp->rx_pause_on);
1442 netdev_info(gp->dev, "Pause is disabled\n");
1449 static int gem_mdio_link_not_up(struct gem *gp)
1451 switch (gp->lstate) {
1453 netif_info(gp, link, gp->dev,
1455 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1456 gp->last_forced_speed, DUPLEX_HALF);
1457 gp->timer_ticks = 5;
1458 gp->lstate = link_force_ok;
1465 if (gp->phy_mii.def->magic_aneg)
1467 netif_info(gp, link, gp->dev, "switching to forced 100bt\n");
1469 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1471 gp->timer_ticks = 5;
1472 gp->lstate = link_force_try;
1479 if (gp->phy_mii.speed == SPEED_100) {
1480 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1482 gp->timer_ticks = 5;
1483 netif_info(gp, link, gp->dev,
1495 struct gem *gp = from_timer(gp, t, link_timer);
1496 struct net_device *dev = gp->dev;
1500 if (gp->reset_task_pending)
1503 if (gp->phy_type == phy_serialink ||
1504 gp->phy_type == phy_serdes) {
1505 u32 val = readl(gp->regs + PCS_MIISTAT);
1508 val = readl(gp->regs + PCS_MIISTAT);
1511 if (gp->lstate == link_up)
1514 gp->lstate = link_up;
1516 (void)gem_set_link_modes(gp);
1520 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1526 if (gp->lstate == link_force_try && gp->want_autoneg) {
1527 gp->lstate = link_force_ret;
1528 gp->last_forced_speed = gp->phy_mii.speed;
1529 gp->timer_ticks = 5;
1530 if (netif_msg_link(gp))
1533 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1534 } else if (gp->lstate != link_up) {
1535 gp->lstate = link_up;
1537 if (gem_set_link_modes(gp))
1544 if (gp->lstate == link_up) {
1545 gp->lstate = link_down;
1546 netif_info(gp, link, dev, "Link down\n");
1548 gem_schedule_reset(gp);
1551 } else if (++gp->timer_ticks > 10) {
1552 if (found_mii_phy(gp))
1553 restart_aneg = gem_mdio_link_not_up(gp);
1559 gem_begin_auto_negotiation(gp, NULL);
1563 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1566 static void gem_clean_rings(struct gem *gp)
1568 struct gem_init_block *gb = gp->init_block;
1577 if (gp->rx_skbs[i] != NULL) {
1578 skb = gp->rx_skbs[i];
1580 dma_unmap_page(&gp->pdev->dev, dma_addr,
1581 RX_BUF_ALLOC_SIZE(gp),
1584 gp->rx_skbs[i] = NULL;
1592 if (gp->tx_skbs[i] != NULL) {
1596 skb = gp->tx_skbs[i];
1597 gp->tx_skbs[i] = NULL;
1604 dma_unmap_page(&gp->pdev->dev, dma_addr,
1616 static void gem_init_rings(struct gem *gp)
1618 struct gem_init_block *gb = gp->init_block;
1619 struct net_device *dev = gp->dev;
1623 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1625 gem_clean_rings(gp);
1627 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1634 skb = gem_alloc_skb(dev, RX_BUF_ALLOC_SIZE(gp), GFP_KERNEL);
1641 gp->rx_skbs[i] = skb;
1642 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1643 dma_addr = dma_map_page(&gp->pdev->dev,
1646 RX_BUF_ALLOC_SIZE(gp),
1650 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1665 static void gem_init_phy(struct gem *gp)
1670 mifcfg = readl(gp->regs + MIF_CFG);
1672 writel(mifcfg, gp->regs + MIF_CFG);
1674 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1683 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1689 sungem_phy_write(gp, MII_BMCR, BMCR_RESET);
1691 if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
1694 netdev_warn(gp->dev, "GMAC PHY not responding !\n");
1698 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1699 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1703 if (gp->phy_type == phy_mii_mdio0 ||
1704 gp->phy_type == phy_mii_mdio1) {
1706 } else if (gp->phy_type == phy_serialink) {
1712 writel(val, gp->regs + PCS_DMODE);
1715 if (gp->phy_type == phy_mii_mdio0 ||
1716 gp->phy_type == phy_mii_mdio1) {
1718 sungem_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1721 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1722 gp->phy_mii.def->ops->init(&gp->phy_mii);
1724 gem_pcs_reset(gp);
1725 gem_pcs_reinit_adv(gp);
1729 gp->timer_ticks = 0;
1730 gp->lstate = link_down;
1731 netif_carrier_off(gp->dev);
1734 if (gp->phy_type == phy_mii_mdio0 ||
1735 gp->phy_type == phy_mii_mdio1)
1736 netdev_info(gp->dev, "Found %s PHY\n",
1737 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
1739 gem_begin_auto_negotiation(gp, NULL);
1742 static void gem_init_dma(struct gem *gp)
1744 u64 desc_dma = (u64) gp->gblock_dvma;
1748 writel(val, gp->regs + TXDMA_CFG);
1750 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1751 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1754 writel(0, gp->regs + TXDMA_KICK);
1758 writel(val, gp->regs + RXDMA_CFG);
1760 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1761 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1763 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1765 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1766 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1767 writel(val, gp->regs + RXDMA_PTHRESH);
1769 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1772 gp->regs + RXDMA_BLANK);
1776 gp->regs + RXDMA_BLANK);
1779 static u32 gem_setup_multicast(struct gem *gp)
1784 if ((gp->dev->flags & IFF_ALLMULTI) ||
1785 (netdev_mc_count(gp->dev) > 256)) {
1787 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1789 } else if (gp->dev->flags & IFF_PROMISC) {
1798 netdev_for_each_mc_addr(ha, gp->dev) {
1804 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1811 static void gem_init_mac(struct gem *gp)
1813 unsigned char *e = &gp->dev->dev_addr[0];
1815 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1817 writel(0x00, gp->regs + MAC_IPG0);
1818 writel(0x08, gp->regs + MAC_IPG1);
1819 writel(0x04, gp->regs + MAC_IPG2);
1820 writel(0x40, gp->regs + MAC_STIME);
1821 writel(0x40, gp->regs + MAC_MINFSZ);
1824 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1826 writel(0x07, gp->regs + MAC_PASIZE);
1827 writel(0x04, gp->regs + MAC_JAMSIZE);
1828 writel(0x10, gp->regs + MAC_ATTLIM);
1829 writel(0x8808, gp->regs + MAC_MCTYPE);
1831 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1833 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1834 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1835 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1837 writel(0, gp->regs + MAC_ADDR3);
1838 writel(0, gp->regs + MAC_ADDR4);
1839 writel(0, gp->regs + MAC_ADDR5);
1841 writel(0x0001, gp->regs + MAC_ADDR6);
1842 writel(0xc200, gp->regs + MAC_ADDR7);
1843 writel(0x0180, gp->regs + MAC_ADDR8);
1845 writel(0, gp->regs + MAC_AFILT0);
1846 writel(0, gp->regs + MAC_AFILT1);
1847 writel(0, gp->regs + MAC_AFILT2);
1848 writel(0, gp->regs + MAC_AF21MSK);
1849 writel(0, gp->regs + MAC_AF0MSK);
1851 gp->mac_rx_cfg = gem_setup_multicast(gp);
1853 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1855 writel(0, gp->regs + MAC_NCOLL);
1856 writel(0, gp->regs + MAC_FASUCC);
1857 writel(0, gp->regs + MAC_ECOLL);
1858 writel(0, gp->regs + MAC_LCOLL);
1859 writel(0, gp->regs + MAC_DTIMER);
1860 writel(0, gp->regs + MAC_PATMPS);
1861 writel(0, gp->regs + MAC_RFCTR);
1862 writel(0, gp->regs + MAC_LERR);
1863 writel(0, gp->regs + MAC_AERR);
1864 writel(0, gp->regs + MAC_FCSERR);
1865 writel(0, gp->regs + MAC_RXCVERR);
1870 writel(0, gp->regs + MAC_TXCFG);
1871 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1872 writel(0, gp->regs + MAC_MCCFG);
1873 writel(0, gp->regs + MAC_XIFCFG);
1879 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1880 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1885 writel(0xffffffff, gp->regs + MAC_MCMASK);
1889 if (gp->has_wol)
1890 writel(0, gp->regs + WOL_WAKECSR);
1893 static void gem_init_pause_thresholds(struct gem *gp)
1902 if (gp->rx_fifo_sz <= (2 * 1024)) {
1903 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1905 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1906 int off = (gp->rx_fifo_sz - (max_frame * 2));
1909 gp->rx_pause_off = off;
1910 gp->rx_pause_on = on;
1918 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1925 writel(cfg, gp->regs + GREG_CFG);
1930 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1933 writel(cfg, gp->regs + GREG_CFG);
1937 static int gem_check_invariants(struct gem *gp)
1939 struct pci_dev *pdev = gp->pdev;
1947 gp->phy_type = phy_mii_mdio0;
1948 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1949 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1950 gp->swrst_base = 0;
1952 mif_cfg = readl(gp->regs + MIF_CFG);
1955 writel(mif_cfg, gp->regs + MIF_CFG);
1956 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
1957 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
1963 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
1964 gp->mii_phy_addr = 1;
1966 gp->mii_phy_addr = 0;
1971 mif_cfg = readl(gp->regs + MIF_CFG);
1990 gp->phy_type = phy_mii_mdio1;
1992 writel(mif_cfg, gp->regs + MIF_CFG);
1994 gp->phy_type = phy_mii_mdio0;
1996 writel(mif_cfg, gp->regs + MIF_CFG);
2001 p = of_get_property(gp->of_node, "shared-pins", NULL);
2003 gp->phy_type = phy_serdes;
2006 gp->phy_type = phy_serialink;
2008 if (gp->phy_type == phy_mii_mdio1 ||
2009 gp->phy_type == phy_mii_mdio0) {
2013 gp->mii_phy_addr = i;
2014 if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
2022 gp->phy_type = phy_serdes;
2027 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2028 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2032 if (gp->tx_fifo_sz != (9 * 1024) ||
2033 gp->rx_fifo_sz != (20 * 1024)) {
2035 gp->tx_fifo_sz, gp->rx_fifo_sz);
2038 gp->swrst_base = 0;
2040 if (gp->tx_fifo_sz != (2 * 1024) ||
2041 gp->rx_fifo_sz != (2 * 1024)) {
2043 gp->tx_fifo_sz, gp->rx_fifo_sz);
2046 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2053 static void gem_reinit_chip(struct gem *gp)
2056 gem_reset(gp);
2059 gem_disable_ints(gp);
2062 gem_init_rings(gp);
2065 gem_init_pause_thresholds(gp);
2068 gem_init_dma(gp);
2069 gem_init_mac(gp);
2073 static void gem_stop_phy(struct gem *gp, int wol)
2085 mifcfg = readl(gp->regs + MIF_CFG);
2087 writel(mifcfg, gp->regs + MIF_CFG);
2089 if (wol && gp->has_wol) {
2090 unsigned char *e = &gp->dev->dev_addr[0];
2095 gp->regs + MAC_RXCFG);
2096 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2097 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2098 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2100 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2102 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2104 writel(csr, gp->regs + WOL_WAKECSR);
2106 writel(0, gp->regs + MAC_RXCFG);
2107 (void)readl(gp->regs + MAC_RXCFG);
2115 writel(0, gp->regs + MAC_TXCFG);
2116 writel(0, gp->regs + MAC_XIFCFG);
2117 writel(0, gp->regs + TXDMA_CFG);
2118 writel(0, gp->regs + RXDMA_CFG);
2121 gem_reset(gp);
2122 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2123 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2125 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2126 gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2131 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2132 writel(0, gp->regs + MIF_BBCLK);
2133 writel(0, gp->regs + MIF_BBDATA);
2134 writel(0, gp->regs + MIF_BBOENAB);
2135 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2136 (void) readl(gp->regs + MAC_XIFCFG);
2142 struct gem *gp = netdev_priv(dev);
2145 pci_set_master(gp->pdev);
2148 gem_reinit_chip(gp);
2151 rc = request_irq(gp->pdev->irq, gem_interrupt,
2156 gem_reset(gp);
2157 gem_clean_rings(gp);
2158 gem_put_cell(gp);
2168 gem_netif_start(gp);
2174 gem_init_phy(gp);
2181 struct gem *gp = netdev_priv(dev);
2184 gem_netif_stop(gp);
2191 gem_disable_ints(gp);
2194 del_timer_sync(&gp->link_timer);
2205 gp->reset_task_pending = 0;
2208 gem_stop_dma(gp);
2211 gem_reset(gp);
2215 gem_clean_rings(gp);
2218 free_irq(gp->pdev->irq, (void *) dev);
2221 gem_stop_phy(gp, wol);
2226 struct gem *gp = container_of(work, struct gem, reset_task);
2236 if (!netif_device_present(gp->dev) ||
2237 !netif_running(gp->dev) ||
2238 !gp->reset_task_pending) {
2244 del_timer_sync(&gp->link_timer);
2247 gem_netif_stop(gp);
2250 gem_reinit_chip(gp);
2251 if (gp->lstate == link_up)
2252 gem_set_link_modes(gp);
2255 gem_netif_start(gp);
2258 gp->reset_task_pending = 0;
2263 if (gp->lstate != link_up)
2264 gem_begin_auto_negotiation(gp, NULL);
2266 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
2273 struct gem *gp = netdev_priv(dev);
2281 gem_get_cell(gp);
2284 rc = pci_enable_device(gp->pdev);
2291 gem_put_cell(gp);
2302 struct gem *gp = netdev_priv(dev);
2308 pci_disable_device(gp->pdev);
2311 if (!gp->asleep_wol)
2312 gem_put_cell(gp);
2320 struct gem *gp = netdev_priv(dev);
2336 (gp->wake_on_lan && netif_running(dev)) ?
2345 gp->asleep_wol = !!gp->wake_on_lan;
2346 gem_do_stop(dev, gp->asleep_wol);
2349 if (!gp->asleep_wol)
2350 gem_put_cell(gp);
2361 struct gem *gp = netdev_priv(dev);
2376 gem_get_cell(gp);
2386 if (gp->asleep_wol)
2387 gem_put_cell(gp);
2397 struct gem *gp = netdev_priv(dev);
2410 if (WARN_ON(!gp->cell_enabled))
2413 dev->stats.rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2414 writel(0, gp->regs + MAC_FCSERR);
2416 dev->stats.rx_frame_errors += readl(gp->regs + MAC_AERR);
2417 writel(0, gp->regs + MAC_AERR);
2419 dev->stats.rx_length_errors += readl(gp->regs + MAC_LERR);
2420 writel(0, gp->regs + MAC_LERR);
2422 dev->stats.tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2424 (readl(gp->regs + MAC_ECOLL) + readl(gp->regs + MAC_LCOLL));
2425 writel(0, gp->regs + MAC_ECOLL);
2426 writel(0, gp->regs + MAC_LCOLL);
2434 struct gem *gp = netdev_priv(dev);
2447 if (WARN_ON(!gp->cell_enabled))
2450 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
2451 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
2452 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
2459 struct gem *gp = netdev_priv(dev);
2467 if (gp->reset_task_pending || WARN_ON(!gp->cell_enabled))
2470 rxcfg = readl(gp->regs + MAC_RXCFG);
2471 rxcfg_new = gem_setup_multicast(gp);
2475 gp->mac_rx_cfg = rxcfg_new;
2477 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2478 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2487 writel(rxcfg, gp->regs + MAC_RXCFG);
2500 struct gem *gp = netdev_priv(dev);
2509 if (WARN_ON(!gp->cell_enabled))
2512 gem_netif_stop(gp);
2513 gem_reinit_chip(gp);
2514 if (gp->lstate == link_up)
2515 gem_set_link_modes(gp);
2516 gem_netif_start(gp);
2523 struct gem *gp = netdev_priv(dev);
2527 strlcpy(info->bus_info, pci_name(gp->pdev), sizeof(info->bus_info));
2533 struct gem *gp = netdev_priv(dev);
2536 if (gp->phy_type == phy_mii_mdio0 ||
2537 gp->phy_type == phy_mii_mdio1) {
2538 if (gp->phy_mii.def)
2539 supported = gp->phy_mii.def->features;
2549 cmd->base.autoneg = gp->want_autoneg;
2550 cmd->base.speed = gp->phy_mii.speed;
2551 cmd->base.duplex = gp->phy_mii.duplex;
2552 advertising = gp->phy_mii.advertising;
2573 if (gp->phy_type == phy_serdes) {
2580 if (gp->lstate == link_up)
2598 struct gem *gp = netdev_priv(dev);
2623 if (netif_device_present(gp->dev)) {
2624 del_timer_sync(&gp->link_timer);
2625 gem_begin_auto_negotiation(gp, cmd);
2633 struct gem *gp = netdev_priv(dev);
2635 if (!gp->want_autoneg)
2639 if (netif_device_present(gp->dev)) {
2640 del_timer_sync(&gp->link_timer);
2641 gem_begin_auto_negotiation(gp, NULL);
2649 struct gem *gp = netdev_priv(dev);
2650 return gp->msg_enable;
2655 struct gem *gp = netdev_priv(dev);
2656 gp->msg_enable = value;
2667 struct gem *gp = netdev_priv(dev);
2670 if (gp->has_wol) {
2672 wol->wolopts = gp->wake_on_lan;
2681 struct gem *gp = netdev_priv(dev);
2683 if (!gp->has_wol)
2685 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2703 struct gem *gp = netdev_priv(dev);
2714 data->phy_id = gp->mii_phy_addr;
2718 data->val_out = __sungem_phy_read(gp, data->phy_id & 0x1f,
2724 __sungem_phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2784 static int gem_get_device_address(struct gem *gp)
2787 struct net_device *dev = gp->dev;
2790 addr = of_get_property(gp->of_node, "local-mac-address", NULL);
2802 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2812 struct gem *gp = netdev_priv(dev);
2817 cancel_work_sync(&gp->reset_task);
2821 gp->init_block, gp->gblock_dvma);
2822 iounmap(gp->regs);
2848 struct gem *gp;
2897 dev = alloc_etherdev(sizeof(*gp));
2904 gp = netdev_priv(dev);
2912 gp->pdev = pdev;
2913 gp->dev = dev;
2915 gp->msg_enable = DEFAULT_MSG;
2917 timer_setup(&gp->link_timer, gem_link_timer, 0);
2919 INIT_WORK(&gp->reset_task, gem_reset_task);
2921 gp->lstate = link_down;
2922 gp->timer_ticks = 0;
2925 gp->regs = ioremap(gemreg_base, gemreg_len);
2926 if (!gp->regs) {
2936 gp->of_node = pci_device_to_OF_node(pdev);
2941 gp->has_wol = 1;
2944 gem_get_cell(gp);
2947 gem_reset(gp);
2950 gp->phy_mii.dev = dev;
2951 gp->phy_mii.mdio_read = _sungem_phy_read;
2952 gp->phy_mii.mdio_write = _sungem_phy_write;
2954 gp->phy_mii.platform_data = gp->of_node;
2957 gp->want_autoneg = 1;
2960 if (gem_check_invariants(gp)) {
2968 gp->init_block = dma_alloc_coherent(&pdev->dev, sizeof(struct gem_init_block),
2969 &gp->gblock_dvma, GFP_KERNEL);
2970 if (!gp->init_block) {
2976 err = gem_get_device_address(gp);
2981 netif_napi_add(dev, &gp->napi, gem_poll, 64);
3010 gem_put_cell(gp);
3020 gem_put_cell(gp);
3021 iounmap(gp->regs);