Lines Matching defs:FZC_MAC
12 #define FZC_MAC 0x180000UL
125 #define XMAC_PORT0_OFF (FZC_MAC + 0x000000)
126 #define XMAC_PORT1_OFF (FZC_MAC + 0x006000)
127 #define BMAC_PORT2_OFF (FZC_MAC + 0x00c000)
128 #define BMAC_PORT3_OFF (FZC_MAC + 0x010000)
593 #define XPCS_CONTROL1 (FZC_MAC + 0x00000UL)
601 #define XPCS_STATUS1 (FZC_MAC + 0x00008UL)
606 #define XPCS_DEVICE_IDENTIFIER (FZC_MAC + 0x00010UL)
609 #define XPCS_SPEED_ABILITY (FZC_MAC + 0x00018UL)
612 #define XPCS_DEV_IN_PKG (FZC_MAC + 0x00020UL)
622 #define XPCS_CONTROL2 (FZC_MAC + 0x00028UL)
625 #define XPCS_STATUS2 (FZC_MAC + 0x00030UL)
633 #define XPCS_PKG_ID (FZC_MAC + 0x00038UL)
636 #define XPCS_STATUS(IDX) (FZC_MAC + 0x00040UL)
644 #define XPCS_TEST_CONTROL (FZC_MAC + 0x00048UL)
648 #define XPCS_CFG_VENDOR1 (FZC_MAC + 0x00050UL)
655 #define XPCS_DIAG_VENDOR2 (FZC_MAC + 0x00058UL)
663 #define XPCS_MASK1 (FZC_MAC + 0x00060UL)
667 #define XPCS_PKT_COUNT (FZC_MAC + 0x00068UL)
671 #define XPCS_TX_SM (FZC_MAC + 0x00070UL)
674 #define XPCS_DESKEW_ERR_CNT (FZC_MAC + 0x00078UL)
677 #define XPCS_SYMERR_CNT01 (FZC_MAC + 0x00080UL)
681 #define XPCS_SYMERR_CNT23 (FZC_MAC + 0x00088UL)
685 #define XPCS_TRAINING_VECTOR (FZC_MAC + 0x00090UL)
690 #define PCS_MII_CTL (FZC_MAC + 0x00000UL)
701 #define PCS_MII_STAT (FZC_MAC + 0x00008UL)
710 #define PCS_MII_ADV (FZC_MAC + 0x00010UL)
719 #define PCS_MII_PARTNER (FZC_MAC + 0x00018UL)
727 #define PCS_CONF (FZC_MAC + 0x00020UL)
735 #define PCS_STATE (FZC_MAC + 0x00028UL)
750 #define PCS_INTERRUPT (FZC_MAC + 0x00030UL)
753 #define PCS_DPATH_MODE (FZC_MAC + 0x000a0UL)
758 #define PCS_PKT_CNT (FZC_MAC + 0x000c0UL)
762 #define MIF_BB_MDC (FZC_MAC + 0x16000UL)
765 #define MIF_BB_MDO (FZC_MAC + 0x16008UL)
768 #define MIF_BB_MDO_EN (FZC_MAC + 0x16010UL)
771 #define MIF_FRAME_OUTPUT (FZC_MAC + 0x16018UL)
826 #define MIF_CONFIG (FZC_MAC + 0x16020UL)
836 #define MIF_POLL_STATUS (FZC_MAC + 0x16028UL)
840 #define MIF_POLL_MASK (FZC_MAC + 0x16030UL)
843 #define MIF_SM (FZC_MAC + 0x16038UL)
854 #define MIF_STATUS (FZC_MAC + 0x16040UL)
858 #define MIF_MASK (FZC_MAC + 0x16048UL)
866 #define ENET_SERDES_RESET (FZC_MAC + 0x14000UL)
870 #define ENET_SERDES_CFG (FZC_MAC + 0x14008UL)
874 #define ENET_SERDES_0_PLL_CFG (FZC_MAC + 0x14010UL)
883 #define ENET_SERDES_0_CTRL_CFG (FZC_MAC + 0x14018UL)
909 #define ENET_SERDES_0_TEST_CFG (FZC_MAC + 0x14020UL)
924 #define ENET_SERDES_1_PLL_CFG (FZC_MAC + 0x14028UL)
925 #define ENET_SERDES_1_CTRL_CFG (FZC_MAC + 0x14030UL)
926 #define ENET_SERDES_1_TEST_CFG (FZC_MAC + 0x14038UL)
928 #define ENET_RGMII_CFG_REG (FZC_MAC + 0x14040UL)
930 #define ESR_INT_SIGNALS (FZC_MAC + 0x14800UL)
957 #define ESR_DEBUG_SEL (FZC_MAC + 0x14808UL)