Lines Matching refs:val
56 static void writeq(u64 val, void __iomem *reg)
58 writel(val & 0xffffffff, reg);
59 writel(val >> 32, reg + 0x4UL);
73 #define nw64(reg, val) writeq((val), np->regs + (reg))
76 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg))
79 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg))
82 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg))
85 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg))
105 u64 val = nr64_mac(reg);
107 if (!(val & bits))
125 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
140 u64 val = nr64_ipp(reg);
142 if (!(val & bits))
156 u64 val;
158 val = nr64_ipp(reg);
159 val |= bits;
160 nw64_ipp(reg, val);
164 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
179 u64 val = nr64(reg);
181 if (!(val & bits))
204 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n",
217 u64 val = (u64) lp->timer;
220 val |= LDG_IMGMT_ARM;
222 nw64(LDG_IMGMT(lp->ldg_num), val);
228 u64 val;
241 val = nr64(mask_reg);
243 val &= ~bits;
245 val |= bits;
246 nw64(mask_reg, val);
292 static u32 phy_decode(u32 val, int port)
294 return (val >> (port * 2)) & PORT_TYPE_MASK;
300 u64 val;
303 val = nr64(MIF_FRAME_OUTPUT);
304 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1)
305 return val & MIF_FRAME_OUTPUT_DATA;
361 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val)
367 val & 0xffff);
371 val >> 16);
375 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val)
381 val & 0xffff);
385 val >> 16);
432 u64 sig, mask, val;
494 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
495 mask = val;
499 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
500 mask = val;
509 if ((sig & mask) == val)
515 if ((sig & mask) != val) {
517 np->port, (int)(sig & mask), (int)val);
529 u64 sig, mask, val;
589 val = (ESR_INT_SRDY0_P0 |
600 val = (ESR_INT_SRDY0_P1 |
615 if ((sig & mask) == val)
621 if ((sig & mask) != val) {
623 np->port, (int)(sig & mask), (int)val);
639 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val)
645 *val = (err & 0xffff);
649 *val |= ((err & 0xffff) << 16);
655 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val)
662 *val = (err & 0xffff);
666 *val |= ((err & 0xffff) << 16);
673 static int esr_read_reset(struct niu *np, u32 *val)
680 *val = (err & 0xffff);
684 *val |= ((err & 0xffff) << 16);
691 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val)
696 ESR_RXTX_CTRL_L(chan), val & 0xffff);
699 ESR_RXTX_CTRL_H(chan), (val >> 16));
703 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val)
708 ESR_GLUE_CTRL0_L(chan), val & 0xffff);
711 ESR_GLUE_CTRL0_H(chan), (val >> 16));
758 u64 ctrl_val, test_cfg_val, sig, mask, val;
842 val = (ESR_INT_SRDY0_P0 |
853 val = (ESR_INT_SRDY0_P1 |
866 if ((sig & mask) != val) {
872 np->port, (int)(sig & mask), (int)val);
882 u64 val;
884 val = nr64(ENET_SERDES_1_PLL_CFG);
885 val &= ~ENET_SERDES_PLL_FBDIV2;
888 val |= ENET_SERDES_PLL_HRATE0;
891 val |= ENET_SERDES_PLL_HRATE1;
894 val |= ENET_SERDES_PLL_HRATE2;
897 val |= ENET_SERDES_PLL_HRATE3;
902 nw64(ENET_SERDES_1_PLL_CFG, val);
911 u64 ctrl_val, test_cfg_val, sig, mask, val;
915 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 |
964 nw64(pll_cfg, val);
1006 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0);
1007 mask = val;
1011 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1);
1012 mask = val;
1019 if ((sig & mask) != val) {
1021 np->port, (int)(sig & mask), (int)val);
1032 u64 val;
1043 val = nr64_pcs(PCS_MII_STAT);
1045 if (val & PCS_MII_STAT_LINK_STATUS) {
1065 u64 val, val2;
1076 val = nr64_xpcs(XPCS_STATUS(0));
1081 if ((val & 0x1000ULL) && link_ok) {
1374 static int mrvl88x2011_act_led(struct niu *np, int val)
1384 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1538 u64 val;
1544 val = nr64_mac(XMAC_CONFIG);
1545 val &= ~XMAC_CONFIG_LED_POLARITY;
1546 val |= XMAC_CONFIG_FORCE_LED_ON;
1547 nw64_mac(XMAC_CONFIG, val);
1549 val = nr64(MIF_CONFIG);
1550 val |= MIF_CONFIG_INDIRECT_MODE;
1551 nw64(MIF_CONFIG, val);
1598 u64 val;
1600 val = nr64_mac(XMAC_CONFIG);
1601 val &= ~XMAC_CONFIG_LED_POLARITY;
1602 val |= XMAC_CONFIG_FORCE_LED_ON;
1603 nw64_mac(XMAC_CONFIG, val);
1606 val = nr64(MIF_CONFIG);
1607 val |= MIF_CONFIG_INDIRECT_MODE;
1608 nw64(MIF_CONFIG, val);
1656 u64 val;
1659 val = nr64(MIF_CONFIG);
1660 val &= ~MIF_CONFIG_INDIRECT_MODE;
1661 nw64(MIF_CONFIG, val);
1850 u64 val;
1853 val = nr64(MIF_CONFIG);
1854 val &= ~MIF_CONFIG_INDIRECT_MODE;
1855 nw64(MIF_CONFIG, val);
2106 u64 sig, mask, val;
2112 val = (ESR_INT_SRDY0_P0 |
2123 val = (ESR_INT_SRDY0_P1 |
2136 if ((sig & mask) != val)
2354 u64 ctrl_val, test_cfg_val, sig, mask, val;
2439 val = (ESR_INT_SRDY0_P0 |
2450 val = (ESR_INT_SRDY0_P1 |
2463 if ((sig & mask) != val) {
2656 u64 val, mask;
2669 val = nr64_mac(reg);
2671 val |= mask;
2673 val &= ~mask;
2674 nw64_mac(reg, val);
2682 u64 val = nr64_mac(reg);
2683 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR);
2684 val |= num;
2686 val |= HOST_INFO_MPR;
2687 nw64_mac(reg, val);
2859 u64 val = nr64(FFLP_CFG_1);
2862 val &= ~FFLP_CFG_1_TCAM_DIS;
2864 val |= FFLP_CFG_1_TCAM_DIS;
2865 nw64(FFLP_CFG_1, val);
2870 u64 val = nr64(FFLP_CFG_1);
2872 val &= ~(FFLP_CFG_1_FFLPINITDONE |
2875 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT);
2876 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT);
2877 nw64(FFLP_CFG_1, val);
2879 val = nr64(FFLP_CFG_1);
2880 val |= FFLP_CFG_1_FFLPINITDONE;
2881 nw64(FFLP_CFG_1, val);
2888 u64 val;
2895 val = nr64(reg);
2897 val |= L2_CLS_VLD;
2899 val &= ~L2_CLS_VLD;
2900 nw64(reg, val);
2910 u64 val;
2918 val = nr64(reg);
2919 val &= ~L2_CLS_ETYPE;
2920 val |= (ether_type << L2_CLS_ETYPE_SHIFT);
2921 nw64(reg, val);
2931 u64 val;
2938 val = nr64(reg);
2940 val |= L3_CLS_VALID;
2942 val &= ~L3_CLS_VALID;
2943 nw64(reg, val);
2953 u64 val;
2963 val = nr64(reg);
2964 val &= ~(L3_CLS_IPVER | L3_CLS_PID |
2967 val |= L3_CLS_IPVER;
2968 val |= (protocol_id << L3_CLS_PID_SHIFT);
2969 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT);
2970 val |= (tos_val << L3_CLS_TOS_SHIFT);
2971 nw64(reg, val);
3021 u64 val = hash_addr_regval(index, num_entries);
3028 nw64(HASH_TBL_ADDR(partition), val);
3040 u64 val = hash_addr_regval(index, num_entries);
3047 nw64(HASH_TBL_ADDR(partition), val);
3056 u64 val;
3062 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE;
3063 nw64(FFLP_CFG_1, val);
3068 u64 val = nr64(FFLP_CFG_1);
3070 val &= ~FFLP_CFG_1_FFLPINITDONE;
3071 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT);
3072 nw64(FFLP_CFG_1, val);
3074 val = nr64(FFLP_CFG_1);
3075 val |= FFLP_CFG_1_FFLPINITDONE;
3076 nw64(FFLP_CFG_1, val);
3078 val = nr64(FCRAM_REF_TMR);
3079 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN);
3080 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT);
3081 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT);
3082 nw64(FCRAM_REF_TMR, val);
3089 u64 val;
3098 val = nr64(reg);
3099 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE);
3100 val |= (mask << FLW_PRT_SEL_MASK_SHIFT);
3101 val |= (base << FLW_PRT_SEL_BASE_SHIFT);
3103 val |= FLW_PRT_SEL_EXT;
3104 nw64(reg, val);
3123 u64 val = nr64(FFLP_CFG_1);
3126 val |= FFLP_CFG_1_LLCSNAP;
3128 val &= ~FFLP_CFG_1_LLCSNAP;
3129 nw64(FFLP_CFG_1, val);
3134 u64 val = nr64(FFLP_CFG_1);
3137 val &= ~FFLP_CFG_1_ERRORDIS;
3139 val |= FFLP_CFG_1_ERRORDIS;
3140 nw64(FFLP_CFG_1, val);
3372 u64 addr, val;
3377 val = le64_to_cpup(&rp->rcr[index]);
3378 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3382 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3395 if (!(val & RCR_ENTRY_MULTI))
3420 u64 addr, val, off;
3424 val = le64_to_cpup(&rp->rcr[index]);
3426 len = (val & RCR_ENTRY_L2_LEN) >>
3430 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) <<
3434 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >>
3441 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT);
3444 !(val & (RCR_ENTRY_NOPORT |
3449 } else if (!(val & RCR_ENTRY_MULTI))
3464 if (!(val & RCR_ENTRY_MULTI))
3903 u64 val;
3905 val = nr64_mac(XTXMAC_STATUS);
3906 if (val & XTXMAC_STATUS_FRAME_CNT_EXP)
3908 if (val & XTXMAC_STATUS_BYTE_CNT_EXP)
3910 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR)
3912 if (val & XTXMAC_STATUS_TXMAC_OFLOW)
3914 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR)
3916 if (val & XTXMAC_STATUS_TXMAC_UFLOW)
3919 val = nr64_mac(XRXMAC_STATUS);
3920 if (val & XRXMAC_STATUS_LCL_FLT_STATUS)
3922 if (val & XRXMAC_STATUS_RFLT_DET)
3924 if (val & XRXMAC_STATUS_LFLT_CNT_EXP)
3926 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP)
3928 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP)
3930 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP)
3932 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP)
3934 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP)
3936 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP)
3938 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP)
3940 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP)
3942 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP)
3944 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP)
3946 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP)
3948 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP)
3950 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP)
3952 if (val & XRXMAC_STATUS_LENERR_CNT_EXP)
3954 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP)
3956 if (val & XRXMAC_STATUS_RXUFLOW)
3958 if (val & XRXMAC_STATUS_RXOFLOW)
3961 val = nr64_mac(XMAC_FC_STAT);
3962 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE)
3964 if (val & XMAC_FC_STAT_TX_MAC_PAUSE)
3966 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE)
3973 u64 val;
3975 val = nr64_mac(BTXMAC_STATUS);
3976 if (val & BTXMAC_STATUS_UNDERRUN)
3978 if (val & BTXMAC_STATUS_MAX_PKT_ERR)
3980 if (val & BTXMAC_STATUS_BYTE_CNT_EXP)
3982 if (val & BTXMAC_STATUS_FRAME_CNT_EXP)
3985 val = nr64_mac(BRXMAC_STATUS);
3986 if (val & BRXMAC_STATUS_OVERFLOW)
3988 if (val & BRXMAC_STATUS_FRAME_CNT_EXP)
3990 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP)
3992 if (val & BRXMAC_STATUS_CRC_ERR_EXP)
3994 if (val & BRXMAC_STATUS_LEN_ERR_EXP)
3997 val = nr64_mac(BMAC_CTRL_STATUS);
3998 if (val & BMAC_CTRL_STATUS_NOPAUSE)
4000 if (val & BMAC_CTRL_STATUS_PAUSE)
4002 if (val & BMAC_CTRL_STATUS_PAUSE_RECV)
4544 u64 val = nr64(TX_CS(channel));
4545 if (val & TX_CS_SNG_STATE)
4553 u64 val = nr64(TX_CS(channel));
4555 val |= TX_CS_STOP_N_GO;
4556 nw64(TX_CS(channel), val);
4566 u64 val = nr64(TX_CS(channel));
4567 if (!(val & TX_CS_RST))
4575 u64 val = nr64(TX_CS(channel));
4578 val |= TX_CS_RST;
4579 nw64(TX_CS(channel), val);
4590 u64 val;
4600 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4601 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1);
4602 nw64(TX_LOG_PAGE_VLD(channel), val);
4612 u64 val, mask;
4615 val = nr64(TXC_CONTROL);
4618 val |= TXC_CONTROL_ENABLE | mask;
4620 val &= ~mask;
4621 if ((val & ~TXC_CONTROL_ENABLE) == 0)
4622 val &= ~TXC_CONTROL_ENABLE;
4624 nw64(TXC_CONTROL, val);
4631 u64 val;
4634 val = nr64(TXC_INT_MASK);
4635 val &= ~TXC_INT_MASK_VAL(np->port);
4636 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4642 u64 val = 0;
4648 val |= (1 << np->tx_rings[i].tx_channel);
4650 nw64(TXC_PORT_DMA(np->port), val);
4656 u64 val, ring_len;
4687 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) |
4689 nw64(TX_RNG_CFIG(channel), val);
4728 u64 val;
4732 val = PT_DRR_WEIGHT_DEFAULT_10G;
4737 val = PT_DRR_WEIGHT_DEFAULT_1G;
4740 nw64(PT_DRR_WT(np->port), val);
4776 u64 val;
4786 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
4787 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1);
4788 nw64(RX_LOG_PAGE_VLD(channel), val);
4795 u64 val;
4797 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) |
4801 nw64(RDC_RED_PARA(rp->rx_channel), val);
4806 u64 val = 0;
4811 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT);
4814 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT);
4817 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT);
4820 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT);
4825 val |= RBR_CFIG_B_VLD2;
4828 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT);
4831 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT);
4834 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT);
4837 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT);
4843 val |= RBR_CFIG_B_VLD1;
4846 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT);
4849 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT);
4852 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT);
4855 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT);
4861 val |= RBR_CFIG_B_VLD0;
4864 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT);
4867 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT);
4870 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT);
4873 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT);
4880 *ret = val;
4886 u64 val = nr64(RXDMA_CFIG1(channel));
4890 val |= RXDMA_CFIG1_EN;
4892 val &= ~RXDMA_CFIG1_EN;
4893 nw64(RXDMA_CFIG1(channel), val);
4909 u64 val;
4934 err = niu_compute_rbr_cfig_b(rp, &val);
4937 nw64(RBR_CFIG_B(channel), val);
4952 val = nr64(RX_DMA_CTL_STAT(channel));
4953 val |= RX_DMA_CTL_STAT_RBR_EMPTY;
4954 nw64(RX_DMA_CTL_STAT(channel), val);
5122 u64 val = nr64(RESET_CFIFO);
5124 val |= RESET_CFIFO_RST(np->port);
5125 nw64(RESET_CFIFO, val);
5128 val &= ~RESET_CFIFO_RST(np->port);
5129 nw64(RESET_CFIFO, val);
5171 u64 val = nr64_ipp(IPP_CFIG);
5173 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W);
5180 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W);
5201 u64 data[5], rbuf[5], val;
5238 val = nr64_ipp(IPP_CFIG);
5239 val &= ~IPP_CFIG_IP_MAX_PKT;
5240 val |= (IPP_CFIG_IPP_ENABLE |
5245 nw64_ipp(IPP_CFIG, val);
5252 u64 val;
5253 val = nr64_mac(XMAC_CONFIG);
5258 val |= XMAC_CONFIG_LED_POLARITY;
5259 val &= ~XMAC_CONFIG_FORCE_LED_ON;
5261 val |= XMAC_CONFIG_FORCE_LED_ON;
5262 val &= ~XMAC_CONFIG_LED_POLARITY;
5266 nw64_mac(XMAC_CONFIG, val);
5272 u64 val;
5275 val = nr64(MIF_CONFIG);
5276 val |= MIF_CONFIG_ATCA_GE;
5277 nw64(MIF_CONFIG, val);
5280 val = nr64_mac(XMAC_CONFIG);
5281 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5283 val |= XMAC_CONFIG_TX_OUTPUT_EN;
5286 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC;
5287 val |= XMAC_CONFIG_LOOPBACK;
5289 val &= ~XMAC_CONFIG_LOOPBACK;
5293 val &= ~XMAC_CONFIG_LFS_DISABLE;
5295 val |= XMAC_CONFIG_LFS_DISABLE;
5298 val |= XMAC_CONFIG_1G_PCS_BYPASS;
5300 val &= ~XMAC_CONFIG_1G_PCS_BYPASS;
5303 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5306 val |= XMAC_CONFIG_SEL_CLK_25MHZ;
5308 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ;
5310 nw64_mac(XMAC_CONFIG, val);
5312 val = nr64_mac(XMAC_CONFIG);
5313 val &= ~XMAC_CONFIG_MODE_MASK;
5315 val |= XMAC_CONFIG_MODE_XGMII;
5318 val |= XMAC_CONFIG_MODE_GMII;
5320 val |= XMAC_CONFIG_MODE_MII;
5323 nw64_mac(XMAC_CONFIG, val);
5329 u64 val;
5331 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN;
5334 val |= BMAC_XIF_CONFIG_MII_LOOPBACK;
5336 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK;
5339 val |= BMAC_XIF_CONFIG_GMII_MODE;
5341 val &= ~BMAC_XIF_CONFIG_GMII_MODE;
5343 val &= ~(BMAC_XIF_CONFIG_LINK_LED |
5349 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK;
5351 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK;
5353 nw64_mac(BMAC_XIF_CONFIG, val);
5367 u64 val = nr64_pcs(PCS_MII_CTL);
5368 val |= PCS_MII_CTL_RST;
5369 nw64_pcs(PCS_MII_CTL, val);
5370 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) {
5372 val = nr64_pcs(PCS_MII_CTL);
5379 u64 val = nr64_xpcs(XPCS_CONTROL1);
5380 val |= XPCS_CONTROL1_RESET;
5381 nw64_xpcs(XPCS_CONTROL1, val);
5382 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) {
5384 val = nr64_xpcs(XPCS_CONTROL1);
5391 u64 val;
5411 val = nr64_mac(XMAC_CONFIG);
5412 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS;
5413 nw64_mac(XMAC_CONFIG, val);
5417 val = nr64_xpcs(XPCS_CONTROL1);
5419 val |= XPCS_CONTROL1_LOOPBACK;
5421 val &= ~XPCS_CONTROL1_LOOPBACK;
5422 nw64_xpcs(XPCS_CONTROL1, val);
5491 u64 val;
5493 val = nr64_mac(XMAC_MIN);
5494 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE |
5496 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT);
5497 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT);
5498 nw64_mac(XMAC_MIN, val);
5504 val = nr64_mac(XMAC_IPG);
5506 val &= ~XMAC_IPG_IPG_XGMII;
5507 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT);
5509 val &= ~XMAC_IPG_IPG_MII_GMII;
5510 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT);
5512 nw64_mac(XMAC_IPG, val);
5514 val = nr64_mac(XMAC_CONFIG);
5515 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC |
5519 nw64_mac(XMAC_CONFIG, val);
5527 u64 val;
5536 val = nr64_mac(BTXMAC_CONFIG);
5537 val &= ~(BTXMAC_CONFIG_FCS_DISABLE |
5539 nw64_mac(BTXMAC_CONFIG, val);
5621 u64 val;
5634 val = nr64_mac(XMAC_CONFIG);
5635 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE |
5647 val |= (XMAC_CONFIG_HASH_FILTER_EN);
5648 nw64_mac(XMAC_CONFIG, val);
5673 u64 val;
5686 val = nr64_mac(BRXMAC_CONFIG);
5687 val &= ~(BRXMAC_CONFIG_ENABLE |
5694 val |= (BRXMAC_CONFIG_HASH_FILT_EN);
5695 nw64_mac(BRXMAC_CONFIG, val);
5697 val = nr64_mac(BMAC_ADDR_CMPEN);
5698 val |= BMAC_ADDR_CMPEN_EN0;
5699 nw64_mac(BMAC_ADDR_CMPEN, val);
5714 u64 val = nr64_mac(XMAC_CONFIG);
5717 val |= XMAC_CONFIG_TX_ENABLE;
5719 val &= ~XMAC_CONFIG_TX_ENABLE;
5720 nw64_mac(XMAC_CONFIG, val);
5725 u64 val = nr64_mac(BTXMAC_CONFIG);
5728 val |= BTXMAC_CONFIG_ENABLE;
5730 val &= ~BTXMAC_CONFIG_ENABLE;
5731 nw64_mac(BTXMAC_CONFIG, val);
5744 u64 val = nr64_mac(XMAC_CONFIG);
5746 val &= ~(XMAC_CONFIG_HASH_FILTER_EN |
5750 val |= XMAC_CONFIG_HASH_FILTER_EN;
5752 val |= XMAC_CONFIG_PROMISCUOUS;
5755 val |= XMAC_CONFIG_RX_MAC_ENABLE;
5757 val &= ~XMAC_CONFIG_RX_MAC_ENABLE;
5758 nw64_mac(XMAC_CONFIG, val);
5763 u64 val = nr64_mac(BRXMAC_CONFIG);
5765 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN |
5769 val |= BRXMAC_CONFIG_HASH_FILT_EN;
5771 val |= BRXMAC_CONFIG_PROMISC;
5774 val |= BRXMAC_CONFIG_ENABLE;
5776 val &= ~BRXMAC_CONFIG_ENABLE;
5777 nw64_mac(BRXMAC_CONFIG, val);
5890 u64 rd, wr, val;
5907 val = nr64_ipp(IPP_CFIG);
5908 val &= ~(IPP_CFIG_IPP_ENABLE |
5912 nw64_ipp(IPP_CFIG, val);
6552 __be16 val = vp->h_vlan_encapsulated_proto;
6554 eth_proto_inner = be16_to_cpu(val);
6861 u32 offset, len, val;
6881 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6882 memcpy(data, ((char *)&val) + b_offset, b_count);
6888 val = nr64(ESPC_NCR(offset / 4));
6889 memcpy(data, &val, 4);
6895 val = nr64(ESPC_NCR(offset / 4));
6896 memcpy(data, &val, len);
7820 static void niu_led_state_restore(struct niu *np, u64 val)
7823 nw64_mac(XMAC_CONFIG, val);
7825 nw64_mac(BMAC_XIF_CONFIG, val);
7830 u64 val, reg, bit;
7840 val = nr64_mac(reg);
7842 val |= bit;
7844 val &= ~bit;
7845 nw64_mac(reg, val);
7992 u16 val;
7996 val = (err << 8);
8000 val |= (err & 0xff);
8002 return val;
8008 u16 val;
8013 val = (err & 0xff);
8018 val |= (err & 0xff) << 8;
8020 return val;
8359 u64 val, sum;
8362 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8363 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT;
8364 len = val / 4;
8369 "SPROM: Image size %llu\n", (unsigned long long)val);
8373 val = nr64(ESPC_NCR(i));
8374 sum += (val >> 0) & 0xff;
8375 sum += (val >> 8) & 0xff;
8376 sum += (val >> 16) & 0xff;
8377 sum += (val >> 24) & 0xff;
8386 val = nr64(ESPC_PHY_TYPE);
8389 val8 = (val & ESPC_PHY_TYPE_PORT0) >>
8393 val8 = (val & ESPC_PHY_TYPE_PORT1) >>
8397 val8 = (val & ESPC_PHY_TYPE_PORT2) >>
8401 val8 = (val & ESPC_PHY_TYPE_PORT3) >>
8446 val = nr64(ESPC_MAC_ADDR0);
8448 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val);
8449 dev->dev_addr[0] = (val >> 0) & 0xff;
8450 dev->dev_addr[1] = (val >> 8) & 0xff;
8451 dev->dev_addr[2] = (val >> 16) & 0xff;
8452 dev->dev_addr[3] = (val >> 24) & 0xff;
8454 val = nr64(ESPC_MAC_ADDR1);
8456 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val);
8457 dev->dev_addr[4] = (val >> 0) & 0xff;
8458 dev->dev_addr[5] = (val >> 8) & 0xff;
8471 val = nr64(ESPC_MOD_STR_LEN);
8473 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8474 if (val >= 8 * 4)
8477 for (i = 0; i < val; i += 4) {
8485 np->vpd.model[val] = '\0';
8487 val = nr64(ESPC_BD_MOD_STR_LEN);
8489 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val);
8490 if (val >= 4 * 4)
8493 for (i = 0; i < val; i += 4) {
8501 np->vpd.board_model[val] = '\0';
8794 u32 val;
8805 val = (phy_encode(PORT_TYPE_1G, 0) |
8813 val = (phy_encode(PORT_TYPE_10G, 0) |
8819 val = (phy_encode(PORT_TYPE_10G, 0) |
8822 val = (phy_encode(PORT_TYPE_1G, 0) |
8844 val = (phy_encode(PORT_TYPE_10G, 0) |
8851 val = (phy_encode(PORT_TYPE_10G, 0) |
8856 val = phy_encode(PORT_TYPE_10G, np->port);
8870 val = (phy_encode(PORT_TYPE_10G, 0) |
8875 val = (phy_encode(PORT_TYPE_1G, 0) |
8889 val = (phy_encode(PORT_TYPE_1G, 0) |
8902 parent->port_phy = val;