Lines Matching refs:port
287 static u32 phy_encode(u32 type, int port)
289 return type << (port * 2);
292 static u32 phy_decode(u32 val, int port)
294 return (val >> (port * 2)) & PORT_TYPE_MASK;
313 static int mdio_read(struct niu *np, int port, int dev, int reg)
317 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
322 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
326 static int mdio_write(struct niu *np, int port, int dev, int reg, int data)
330 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
335 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
343 static int mii_read(struct niu *np, int port, int reg)
345 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
349 static int mii_write(struct niu *np, int port, int reg, int data)
353 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
365 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
369 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
379 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
383 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
404 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
443 if (np->port == 0)
449 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
459 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
463 np->port, __func__);
469 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
473 np->port, __func__);
492 switch (np->port) {
517 np->port, (int)(sig & mask), (int)val);
541 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
551 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
555 np->port, __func__);
561 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
565 np->port, __func__);
586 switch (np->port) {
623 np->port, (int)(sig & mask), (int)val);
632 np->port);
643 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
646 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
659 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
663 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
677 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
681 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
695 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
698 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
707 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
710 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
720 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
724 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
730 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
736 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
747 np->port, reset);
761 switch (np->port) {
839 switch (np->port) {
872 np->port, (int)(sig & mask), (int)val);
886 switch (np->port) {
918 switch (np->port) {
1004 switch (np->port) {
1021 np->port, (int)(sig & mask), (int)val);
1282 np->port, (err & 0xffff));
1464 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1469 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1475 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1502 np->port);
1505 np->port);
1610 phy_id = phy_decode(np->parent->port_phy, np->port);
1611 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
1646 np->port, err);
1842 np->port, bmcr, bmsr);
2084 phy_id = phy_decode(np->parent->port_phy, np->port);
2085 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port];
2109 switch (np->port) {
2356 switch (np->port) {
2436 switch (np->port) {
2471 np->port);
2504 if (np->port == 0)
2506 if (np->port == 1)
2510 phy_addr_off += np->port;
2527 phy_addr_off += (np->port ^ 0x3);
2546 phy_addr_off += np->port;
2549 if (np->port == 0)
2551 if (np->port == 1)
2559 switch(np->port) {
2571 phy_addr_off = niu_atca_port_num[np->port];
2748 int port, int vpr, int rdc_table)
2754 ENET_VLAN_TBL_SHIFT(port));
2757 ENET_VLAN_TBL_SHIFT(port));
2758 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port));
4457 int i, port, err;
4459 port = np->port;
4461 for (i = 0; i < port; i++) {
4466 num_rx_rings = parent->rxchan_per_port[port];
4467 num_tx_rings = parent->txchan_per_port[port];
4600 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT;
4616 mask = (u64)1 << np->port;
4635 val &= ~TXC_INT_MASK_VAL(np->port);
4636 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port));
4650 nw64(TXC_PORT_DMA(np->port), val);
4709 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port];
4722 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4727 int type = phy_decode(np->parent->port_phy, np->port);
4740 nw64(PT_DRR_WT(np->port), val);
4746 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
4786 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT;
5036 vlan_tbl_write(np, i, np->port,
5080 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5101 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT)));
5124 val |= RESET_CFIFO_RST(np->port);
5128 val &= ~RESET_CFIFO_RST(np->port);
5138 if (np->port == 0 || np->port == 1)
5161 nw64(CFIFO_ECC(np->port), 0);
5205 if (np->port == 0 || np->port == 1)
5473 np->port,
5578 np->port,
5599 np->port,
5618 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
5670 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port];
6005 int port = np->port;
6010 if (port == 0) {
6809 cmd->base.port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP;
7415 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port];
7913 np->port, ldn, ldg,
8330 if (np->port > 1) {
8350 dev->dev_addr[5] += np->port;
8387 switch (np->port) {
8405 dev_err(np->device, "Bogus port number %u\n",
8406 np->port);
8467 dev->dev_addr[5] += np->port;
8515 if (np->port <= 1)
8539 if (np->port >= parent->num_ports)
8582 static int port_has_10g(struct phy_probe_info *p, int port)
8587 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port)
8591 if (p->phy_port[PHY_TYPE_PCS][i] == port)
8600 int port, cnt;
8604 for (port = 8; port < 32; port++) {
8605 if (port_has_10g(p, port)) {
8607 *lowest = port;
8685 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n",
8691 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n",
8751 int port, err;
8758 for (port = 8; port < 32; port++) {
8761 dev_id_1 = mdio_read(np, port,
8763 dev_id_2 = mdio_read(np, port,
8765 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8769 dev_id_1 = mdio_read(np, port,
8771 dev_id_2 = mdio_read(np, port,
8773 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8777 dev_id_1 = mii_read(np, port, MII_PHYSID1);
8778 dev_id_2 = mii_read(np, port, MII_PHYSID2);
8779 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8856 val = phy_encode(PORT_TYPE_10G, np->port);
8896 pr_err("Unsupported port config 10G[%d] 1G[%d]\n",
8943 cp->tcam_top = (u16) np->port;
8978 switch (np->port) {
9008 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port);
9023 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port;
9027 num_irqs = (parent->rxchan_per_port[np->port] +
9028 parent->txchan_per_port[np->port] +
9029 (np->port == 0 ? 3 : 1));
9079 u8 port;
9090 port = np->port;
9105 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9116 * MIF (if port zero)
9117 * SYSERR (if port zero)
9125 LDN_MAC(port));
9133 if (port == 0) {
9157 for (i = 0; i < port; i++)
9159 num_chan = parent->rxchan_per_port[port];
9173 for (i = 0; i < port; i++)
9175 num_chan = parent->txchan_per_port[port];
9511 int port = np->port;
9528 sprintf(port_name, "port%d", port);
9533 p->ports[port] = np;
9545 u8 port = np->port;
9548 BUG_ON(!p || p->ports[port] != np);
9551 "%s() port[%u]\n", __func__, port);
9553 sprintf(port_name, "port%d", port);
9559 p->ports[port] = NULL;
9635 const struct niu_ops *ops, u8 port)
9658 np->port = port;