Lines Matching refs:pll_cfg
430 u16 pll_cfg, pll_sts;
457 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X);
460 ESR2_TI_PLL_CFG_L, pll_cfg);
527 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts;
549 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X);
552 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff);
910 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
923 pll_cfg = ENET_SERDES_0_PLL_CFG;
929 pll_cfg = ENET_SERDES_1_PLL_CFG;
964 nw64(pll_cfg, val);
2353 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i;
2360 pll_cfg = ENET_SERDES_0_PLL_CFG;
2365 pll_cfg = ENET_SERDES_1_PLL_CFG;
2397 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);