Lines Matching refs:nw64
73 #define nw64(reg, val) writeq((val), np->regs + (reg))
201 nw64(reg, bits);
222 nw64(LDG_IMGMT(lp->ldg_num), val);
246 nw64(mask_reg, val);
317 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
322 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev));
330 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg));
335 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data));
345 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg));
353 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data));
799 nw64(ctrl_reg, ctrl_val);
800 nw64(test_cfg_reg, test_cfg_val);
902 nw64(ENET_SERDES_1_PLL_CFG, val);
960 nw64(ENET_SERDES_RESET, reset_val);
964 nw64(pll_cfg, val);
965 nw64(ctrl_reg, ctrl_val);
966 nw64(test_cfg_reg, test_cfg_val);
967 nw64(ENET_SERDES_RESET, val_rd);
1551 nw64(MIF_CONFIG, val);
1608 nw64(MIF_CONFIG, val);
1661 nw64(MIF_CONFIG, val);
1855 nw64(MIF_CONFIG, val);
2397 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2);
2398 nw64(ctrl_reg, ctrl_val);
2399 nw64(test_cfg_reg, test_cfg_val);
2762 nw64(ENET_VLAN_TBL(index), reg_val);
2770 nw64(ENET_VLAN_TBL(i), 0);
2790 nw64(TCAM_KEY_0, 0x00);
2791 nw64(TCAM_KEY_MASK_0, 0xff);
2792 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2803 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index));
2822 nw64(TCAM_KEY_0, key[0]);
2823 nw64(TCAM_KEY_1, key[1]);
2824 nw64(TCAM_KEY_2, key[2]);
2825 nw64(TCAM_KEY_3, key[3]);
2826 nw64(TCAM_KEY_MASK_0, mask[0]);
2827 nw64(TCAM_KEY_MASK_1, mask[1]);
2828 nw64(TCAM_KEY_MASK_2, mask[2]);
2829 nw64(TCAM_KEY_MASK_3, mask[3]);
2830 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index));
2840 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index));
2851 nw64(TCAM_KEY_1, assoc_data);
2852 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index));
2865 nw64(FFLP_CFG_1, val);
2877 nw64(FFLP_CFG_1, val);
2881 nw64(FFLP_CFG_1, val);
2900 nw64(reg, val);
2921 nw64(reg, val);
2943 nw64(reg, val);
2971 nw64(reg, val);
3028 nw64(HASH_TBL_ADDR(partition), val);
3047 nw64(HASH_TBL_ADDR(partition), val);
3049 nw64(HASH_TBL_DATA(partition), data[i]);
3058 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST);
3060 nw64(FFLP_CFG_1, 0);
3063 nw64(FFLP_CFG_1, val);
3072 nw64(FFLP_CFG_1, val);
3076 nw64(FFLP_CFG_1, val);
3082 nw64(FCRAM_REF_TMR, val);
3104 nw64(reg, val);
3129 nw64(FFLP_CFG_1, val);
3140 nw64(FFLP_CFG_1, val);
3191 nw64(H1POLY, 0);
3192 nw64(H2POLY, 0);
3225 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3235 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key);
3358 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending);
3637 * reading nr64() and clearing the counter nw64(). For this
3638 * reason, the number of counter clearings nw64() is
3651 nw64(RXMISC(rx_channel), 0);
3666 nw64(RED_DIS_CNT(rx_channel), 0);
3718 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat);
3741 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0);
3756 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0);
3832 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4080 nw64(RX_DMA_CTL_STAT(rp->rx_channel),
4131 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write);
4162 nw64(LD_IM0(ldn), LD_IM0_MASK);
4174 nw64(LD_IM0(ldn), LD_IM0_MASK);
4556 nw64(TX_CS(channel), val);
4579 nw64(TX_CS(channel), val);
4583 nw64(TX_RING_KICK(channel), 0);
4592 nw64(TX_LOG_MASK1(channel), 0);
4593 nw64(TX_LOG_VAL1(channel), 0);
4594 nw64(TX_LOG_MASK2(channel), 0);
4595 nw64(TX_LOG_VAL2(channel), 0);
4596 nw64(TX_LOG_PAGE_RELO1(channel), 0);
4597 nw64(TX_LOG_PAGE_RELO2(channel), 0);
4598 nw64(TX_LOG_PAGE_HDL(channel), 0);
4602 nw64(TX_LOG_PAGE_VLD(channel), val);
4624 nw64(TXC_CONTROL, val);
4650 nw64(TXC_PORT_DMA(np->port), val);
4670 nw64(TXC_DMA_MAX(channel), rp->max_burst);
4671 nw64(TX_ENT_MSK(channel), 0);
4689 nw64(TX_RNG_CFIG(channel), val);
4697 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32);
4698 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR);
4700 nw64(TX_CS(channel), 0);
4718 nw64(RDC_TBL(this_table, slot),
4722 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]);
4740 nw64(PT_DRR_WT(np->port), val);
4778 nw64(RX_LOG_MASK1(channel), 0);
4779 nw64(RX_LOG_VAL1(channel), 0);
4780 nw64(RX_LOG_MASK2(channel), 0);
4781 nw64(RX_LOG_VAL2(channel), 0);
4782 nw64(RX_LOG_PAGE_RELO1(channel), 0);
4783 nw64(RX_LOG_PAGE_RELO2(channel), 0);
4784 nw64(RX_LOG_PAGE_HDL(channel), 0);
4788 nw64(RX_LOG_PAGE_VLD(channel), val);
4801 nw64(RDC_RED_PARA(rp->rx_channel), val);
4893 nw64(RXDMA_CFIG1(channel), val);
4921 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY);
4922 nw64(RX_DMA_CTL_STAT(channel),
4927 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32);
4928 nw64(RXDMA_CFIG2(channel),
4931 nw64(RBR_CFIG_A(channel),
4937 nw64(RBR_CFIG_B(channel), val);
4938 nw64(RCRCFIG_A(channel),
4941 nw64(RCRCFIG_B(channel),
4950 nw64(RBR_KICK(channel), rp->rbr_index);
4954 nw64(RX_DMA_CTL_STAT(channel), val);
4966 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider);
4967 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL));
5026 nw64(H1POLY, cp->h1_init);
5027 nw64(H2POLY, cp->h2_init);
5071 nw64(ZCP_RAM_DATA0, data[0]);
5072 nw64(ZCP_RAM_DATA1, data[1]);
5073 nw64(ZCP_RAM_DATA2, data[2]);
5074 nw64(ZCP_RAM_DATA3, data[3]);
5075 nw64(ZCP_RAM_DATA4, data[4]);
5076 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL);
5077 nw64(ZCP_RAM_ACC,
5098 nw64(ZCP_RAM_ACC,
5125 nw64(RESET_CFIFO, val);
5129 nw64(RESET_CFIFO, val);
5161 nw64(CFIFO_ECC(np->port), 0);
5162 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL);
5164 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL);
5277 nw64(MIF_CONFIG, val);
5872 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL);
5873 nw64(RX_DMA_CTL_STAT(channel), 0);
6711 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3));
7310 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7322 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1),
7334 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key);
7918 nw64(LDG_NUM(ldn), ldg);
7929 nw64(LDG_TIMER_RES, res);
7941 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector);
7956 nw64(ESPC_PIO_STAT, frame);
7971 nw64(ESPC_PIO_STAT, frame);
9285 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE);
9294 nw64(ESPC_PIO_EN, 0);