Lines Matching defs:nr64
72 #define nr64(reg) readq(np->regs + (reg))
179 u64 val = nr64(reg);
206 (unsigned long long)nr64(reg));
241 val = nr64(mask_reg);
303 val = nr64(MIF_FRAME_OUTPUT);
508 sig = nr64(ESR_INT_SIGNALS);
614 sig = nr64(ESR_INT_SIGNALS);
838 sig = nr64(ESR_INT_SIGNALS);
884 val = nr64(ENET_SERDES_1_PLL_CFG);
962 val_rd = nr64(ENET_SERDES_RESET);
1003 sig = nr64(ESR_INT_SIGNALS);
1549 val = nr64(MIF_CONFIG);
1606 val = nr64(MIF_CONFIG);
1659 val = nr64(MIF_CONFIG);
1853 val = nr64(MIF_CONFIG);
2108 sig = nr64(ESR_INT_SIGNALS);
2435 sig = nr64(ESR_INT_SIGNALS);
2750 u64 reg_val = nr64(ENET_VLAN_TBL(index));
2778 if (nr64(TCAM_CTL) & bit)
2806 key[0] = nr64(TCAM_KEY_0);
2807 key[1] = nr64(TCAM_KEY_1);
2808 key[2] = nr64(TCAM_KEY_2);
2809 key[3] = nr64(TCAM_KEY_3);
2810 mask[0] = nr64(TCAM_KEY_MASK_0);
2811 mask[1] = nr64(TCAM_KEY_MASK_1);
2812 mask[2] = nr64(TCAM_KEY_MASK_2);
2813 mask[3] = nr64(TCAM_KEY_MASK_3);
2843 *data = nr64(TCAM_KEY_1);
2859 u64 val = nr64(FFLP_CFG_1);
2870 u64 val = nr64(FFLP_CFG_1);
2879 val = nr64(FFLP_CFG_1);
2895 val = nr64(reg);
2918 val = nr64(reg);
2938 val = nr64(reg);
2963 val = nr64(reg);
3030 data[i] = nr64(HASH_TBL_DATA(partition));
3068 u64 val = nr64(FFLP_CFG_1);
3074 val = nr64(FFLP_CFG_1);
3078 val = nr64(FCRAM_REF_TMR);
3098 val = nr64(reg);
3123 u64 val = nr64(FFLP_CFG_1);
3134 u64 val = nr64(FFLP_CFG_1);
3637 * reading nr64() and clearing the counter nw64(). For this
3649 misc = nr64(RXMISC(rx_channel));
3664 wred = nr64(RED_DIS_CNT(rx_channel));
3686 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3687 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN;
3816 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel));
3867 cs = nr64(TX_CS(rp->tx_channel));
3868 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel));
3869 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel));
3884 u64 mif_status = nr64(MIF_STATUS);
4048 u64 stat = nr64(SYS_ERR_STAT);
4140 rp->tx_cs = nr64(TX_CS(rp->tx_channel));
4206 v0 = nr64(LDSV0(ldg));
4207 v1 = nr64(LDSV1(ldg));
4208 v2 = nr64(LDSV2(ldg));
4544 u64 val = nr64(TX_CS(channel));
4553 u64 val = nr64(TX_CS(channel));
4566 u64 val = nr64(TX_CS(channel));
4575 u64 val = nr64(TX_CS(channel));
4615 val = nr64(TXC_CONTROL);
4634 val = nr64(TXC_INT_MASK);
4886 u64 val = nr64(RXDMA_CFIG1(channel));
4897 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST)
4952 val = nr64(RX_DMA_CTL_STAT(channel));
5094 (unsigned long long)nr64(ZCP_RAM_ACC));
5107 (unsigned long long)nr64(ZCP_RAM_ACC));
5111 data[0] = nr64(ZCP_RAM_DATA0);
5112 data[1] = nr64(ZCP_RAM_DATA1);
5113 data[2] = nr64(ZCP_RAM_DATA2);
5114 data[3] = nr64(ZCP_RAM_DATA3);
5115 data[4] = nr64(ZCP_RAM_DATA4);
5122 u64 val = nr64(RESET_CFIFO);
5163 (void) nr64(ZCP_INT_STAT);
5275 val = nr64(MIF_CONFIG);
6881 val = nr64(ESPC_NCR((offset - b_offset) / 4));
6888 val = nr64(ESPC_NCR(offset / 4));
6895 val = nr64(ESPC_NCR(offset / 4));
7911 if (nr64(LDG_NUM(ldn)) != ldg) {
7914 (unsigned long long) nr64(LDG_NUM(ldn)));
7960 frame = nr64(ESPC_PIO_STAT);
7975 frame = nr64(ESPC_PIO_STAT);
7985 frame = nr64(ESPC_PIO_STAT);
8362 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ);
8373 val = nr64(ESPC_NCR(i));
8386 val = nr64(ESPC_PHY_TYPE);
8446 val = nr64(ESPC_MAC_ADDR0);
8454 val = nr64(ESPC_MAC_ADDR1);
8471 val = nr64(ESPC_MOD_STR_LEN);
8478 u64 tmp = nr64(ESPC_NCR(5 + (i / 4)));
8487 val = nr64(ESPC_BD_MOD_STR_LEN);
8494 u64 tmp = nr64(ESPC_NCR(14 + (i / 4)));
8504 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL;
8527 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) &