Lines Matching defs:err
120 int err;
123 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay);
124 if (err)
128 return err;
155 int err;
162 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay);
163 if (err)
167 return err;
199 int err;
202 err = __niu_wait_bits_clear(np, reg, bits, limit, delay);
203 if (err)
207 return err;
257 int err;
262 err = niu_ldn_irq_enable(np, i, on);
263 if (err)
264 return err;
275 int err;
277 err = niu_enable_ldn_in_ldg(np, lp, on);
278 if (err)
279 return err;
315 int err;
318 err = mdio_wait(np);
319 if (err < 0)
320 return err;
328 int err;
331 err = mdio_wait(np);
332 if (err < 0)
333 return err;
336 err = mdio_wait(np);
337 if (err < 0)
338 return err;
351 int err;
354 err = mdio_wait(np);
355 if (err < 0)
356 return err;
363 int err;
365 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
368 if (!err)
369 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
372 return err;
377 int err;
379 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
382 if (!err)
383 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
386 return err;
413 int err = esr2_set_tx_cfg(np, i, tx_cfg);
414 if (err)
415 return err;
419 int err = esr2_set_rx_cfg(np, i, rx_cfg);
420 if (err)
421 return err;
435 int err;
459 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
461 if (err) {
464 return err;
469 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
471 if (err) {
474 return err;
481 err = esr2_set_tx_cfg(np, i, tx_cfg);
482 if (err)
483 return err;
487 err = esr2_set_rx_cfg(np, i, rx_cfg);
488 if (err)
489 return err;
531 int err;
551 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
553 if (err) {
556 return err;
561 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR,
563 if (err) {
566 return err;
573 err = esr2_set_tx_cfg(np, i, tx_cfg);
574 if (err)
575 return err;
579 err = esr2_set_rx_cfg(np, i, rx_cfg);
580 if (err)
581 return err;
626 err = serdes_init_niu_1g_serdes(np);
627 if (!err) {
641 int err;
643 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan));
644 if (err >= 0) {
645 *val = (err & 0xffff);
646 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
648 if (err >= 0)
649 *val |= ((err & 0xffff) << 16);
650 err = 0;
652 return err;
657 int err;
659 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
661 if (err >= 0) {
662 *val = (err & 0xffff);
663 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
665 if (err >= 0) {
666 *val |= ((err & 0xffff) << 16);
667 err = 0;
670 return err;
675 int err;
677 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
679 if (err >= 0) {
680 *val = (err & 0xffff);
681 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR,
683 if (err >= 0) {
684 *val |= ((err & 0xffff) << 16);
685 err = 0;
688 return err;
693 int err;
695 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
697 if (!err)
698 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
700 return err;
705 int err;
707 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
709 if (!err)
710 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
712 return err;
718 int err;
720 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
722 if (err)
723 return err;
724 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
726 if (err)
727 return err;
730 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
732 if (err)
733 return err;
736 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR,
738 if (err)
739 return err;
742 err = esr_read_reset(np, &reset);
743 if (err)
744 return err;
759 int err;
806 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
807 if (err)
808 return err;
809 err = esr_read_glue0(np, i, &glue0);
810 if (err)
811 return err;
826 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
827 if (err)
828 return err;
829 err = esr_write_glue0(np, i, glue0);
830 if (err)
831 return err;
834 err = esr_reset(np);
835 if (err)
836 return err;
912 int err;
974 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
975 if (err)
976 return err;
977 err = esr_read_glue0(np, i, &glue0);
978 if (err)
979 return err;
994 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
995 if (err)
996 return err;
997 err = esr_write_glue0(np, i, glue0);
998 if (err)
999 return err;
1096 int err;
1100 err = mii_read(np, np->phy_addr, MII_BMCR);
1101 if (unlikely(err < 0))
1102 return err;
1103 bmcr = err;
1105 err = mii_read(np, np->phy_addr, MII_BMSR);
1106 if (unlikely(err < 0))
1107 return err;
1108 bmsr = err;
1110 err = mii_read(np, np->phy_addr, MII_ADVERTISE);
1111 if (unlikely(err < 0))
1112 return err;
1113 advert = err;
1115 err = mii_read(np, np->phy_addr, MII_LPA);
1116 if (unlikely(err < 0))
1117 return err;
1118 lpa = err;
1121 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1122 if (unlikely(err < 0))
1123 return err;
1124 estatus = err;
1126 err = mii_read(np, np->phy_addr, MII_CTRL1000);
1127 if (unlikely(err < 0))
1128 return err;
1129 ctrl1000 = err;
1131 err = mii_read(np, np->phy_addr, MII_STAT1000);
1132 if (unlikely(err < 0))
1133 return err;
1134 stat1000 = err;
1212 int err, link_up;
1220 err = mii_read(np, np->phy_addr, MII_BMSR);
1221 if (err < 0)
1224 bmsr = err;
1232 err = 0;
1238 return err;
1245 int err;
1249 err = link_status_mii(np, link_up_p);
1254 return err;
1259 int err, limit;
1261 err = mdio_read(np, np->phy_addr,
1263 if (err < 0 || err == 0xffff)
1264 return err;
1265 err |= BMCR_RESET;
1266 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1267 MII_BMCR, err);
1268 if (err)
1269 return err;
1273 err = mdio_read(np, np->phy_addr,
1275 if (err < 0)
1276 return err;
1277 if (!(err & BMCR_RESET))
1282 np->port, (err & 0xffff));
1293 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1294 if (err < 0)
1295 return err;
1296 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg);
1297 if (err < 0)
1298 return err;
1304 int err;
1307 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1309 if (err < 0)
1310 return err;
1311 err &= ~USER_ODIG_CTRL_GPIOS;
1312 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1313 err |= USER_ODIG_CTRL_RESV2;
1314 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1315 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1316 if (err)
1317 return err;
1326 int err;
1328 err = mdio_write(np, np->phy_addr,
1339 if (err)
1340 return err;
1342 err = mdio_write(np, np->phy_addr,
1348 if (err)
1349 return err;
1351 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL);
1352 if (err)
1353 return err;
1354 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL);
1355 if (err)
1356 return err;
1358 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1360 if (err < 0)
1361 return err;
1362 err &= ~USER_ODIG_CTRL_GPIOS;
1363 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT);
1364 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1365 BCM8704_USER_OPT_DIGITAL_CTRL, err);
1366 if (err)
1367 return err;
1376 int err;
1378 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1380 if (err < 0)
1381 return err;
1383 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK);
1384 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val);
1387 MRVL88X2011_LED_8_TO_11_CTL, err);
1392 int err;
1394 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1396 if (err >= 0) {
1397 err &= ~MRVL88X2011_LED_BLKRATE_MASK;
1398 err |= (rate << 4);
1400 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR,
1401 MRVL88X2011_LED_BLINK_CTL, err);
1404 return err;
1409 int err;
1412 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS);
1413 if (err)
1414 return err;
1417 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF);
1418 if (err)
1419 return err;
1421 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1423 if (err < 0)
1424 return err;
1426 err |= MRVL88X2011_ENA_XFPREFCLK;
1428 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1429 MRVL88X2011_GENERAL_CTL, err);
1430 if (err < 0)
1431 return err;
1433 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1435 if (err < 0)
1436 return err;
1439 err |= MRVL88X2011_LOOPBACK;
1441 err &= ~MRVL88X2011_LOOPBACK;
1443 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1444 MRVL88X2011_PMA_PMD_CTL_1, err);
1445 if (err < 0)
1446 return err;
1457 int err = 0;
1460 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1462 if (err < 0)
1463 return err;
1464 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err);
1466 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20);
1467 if (err < 0)
1468 return err;
1469 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err);
1471 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
1473 if (err < 0)
1474 return err;
1475 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err);
1479 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1481 if (err < 0)
1482 return err;
1483 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1485 if (err < 0)
1486 return err;
1487 analog_stat0 = err;
1489 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1491 if (err < 0)
1492 return err;
1493 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR,
1495 if (err < 0)
1496 return err;
1497 tx_alarm_status = err;
1515 int err;
1517 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1519 if (err < 0)
1520 return err;
1522 err &= ~BMCR_LOOPBACK;
1525 err |= BMCR_LOOPBACK;
1527 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1528 MII_BMCR, err);
1529 if (err)
1530 return err;
1537 int err = 0;
1542 return err;
1553 err = bcm8704_reset(np);
1554 if (err)
1555 return err;
1557 err = xcvr_10g_set_lb_bcm870x(np);
1558 if (err)
1559 return err;
1561 err = bcm8706_init_user_dev3(np);
1562 if (err)
1563 return err;
1565 err = xcvr_diag_bcm870x(np);
1566 if (err)
1567 return err;
1574 int err;
1576 err = bcm8704_reset(np);
1577 if (err)
1578 return err;
1580 err = bcm8704_init_user_dev3(np);
1581 if (err)
1582 return err;
1584 err = xcvr_10g_set_lb_bcm870x(np);
1585 if (err)
1586 return err;
1588 err = xcvr_diag_bcm870x(np);
1589 if (err)
1590 return err;
1597 int phy_id, err;
1616 err = xcvr_init_10g_mrvl88x2011(np);
1620 err = xcvr_init_10g_bcm8704(np);
1624 return err;
1629 int limit, err;
1631 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET);
1632 if (err)
1633 return err;
1638 err = mii_read(np, np->phy_addr, MII_BMCR);
1639 if (err < 0)
1640 return err;
1641 if (!(err & BMCR_RESET))
1646 np->port, err);
1655 int err;
1663 err = mii_reset(np);
1664 if (err)
1665 return err;
1667 err = mii_read(np, np->phy_addr, MII_BMSR);
1668 if (err < 0)
1669 return err;
1670 bmsr = err;
1674 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1675 if (err < 0)
1676 return err;
1677 estat = err;
1681 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1682 if (err)
1683 return err;
1690 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000);
1691 if (err)
1692 return err;
1697 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1698 if (err)
1699 return err;
1701 err = mii_read(np, np->phy_addr, MII_BMCR);
1702 if (err < 0)
1703 return err;
1706 err = mii_read(np, np->phy_addr, MII_BMSR);
1707 if (err < 0)
1708 return err;
1717 int err;
1719 err = mii_reset(np);
1720 if (err)
1721 return err;
1723 err = mii_read(np, np->phy_addr, MII_BMSR);
1724 if (err < 0)
1725 return err;
1726 bmsr = err;
1730 err = mii_read(np, np->phy_addr, MII_ESTATUS);
1731 if (err < 0)
1732 return err;
1733 estat = err;
1737 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1738 if (err)
1739 return err;
1754 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux);
1755 if (err)
1756 return err;
1775 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv);
1776 if (err)
1777 return err;
1787 err = mii_write(np, np->phy_addr,
1789 if (err)
1790 return err;
1826 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr);
1827 if (err)
1828 return err;
1831 err = mii_read(np, np->phy_addr, MII_BMCR);
1832 if (err < 0)
1833 return err;
1834 bmcr = err;
1836 err = mii_read(np, np->phy_addr, MII_BMSR);
1837 if (err < 0)
1838 return err;
1839 bmsr = err;
1863 int err;
1865 err = 0;
1867 err = ops->xcvr_init(np);
1869 return err;
1875 int err;
1877 err = 0;
1879 err = ops->serdes_init(np);
1881 return err;
1920 int err, link_up, pma_status, pcs_status;
1924 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1926 if (err < 0)
1930 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR,
1932 if (err < 0)
1935 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1938 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1940 if (err < 0)
1943 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR,
1945 if (err < 0)
1948 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0);
1951 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR,
1953 if (err < 0)
1956 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 |
1964 err = 0;
1971 return err;
1976 int err, link_up;
1979 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
1981 if (err < 0 || err == 0xffff)
1983 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
1984 err = 0;
1988 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
1990 if (err < 0)
1993 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
1994 err = 0;
1998 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2000 if (err < 0)
2002 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2009 err = 0;
2018 err = 0;
2022 return err;
2027 int err, link_up;
2031 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR,
2033 if (err < 0)
2035 if (!(err & PMD_RCV_SIGDET_GLOBAL)) {
2036 err = 0;
2040 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR,
2042 if (err < 0)
2044 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) {
2045 err = 0;
2049 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR,
2051 if (err < 0)
2054 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED |
2060 err = 0;
2067 err = 0;
2071 return err;
2077 int err = -EINVAL;
2090 err = link_status_10g_mrvl(np, link_up_p);
2094 err = link_status_10g_bcom(np, link_up_p);
2101 return err;
2144 int err = 0;
2160 err = np->phy_ops->xcvr_init(np);
2161 if (err) {
2162 err = mdio_read(np, np->phy_addr,
2164 if (err == 0xffff) {
2180 err = link_status_10g_bcm8706(np, link_up_p);
2181 if (err == 0xffff) {
2198 int err;
2200 err = 0;
2202 err = ops->link_status(np, link_up_p);
2204 return err;
2211 int err, link_up;
2213 err = niu_link_status(np, &link_up);
2214 if (!err)
2404 int err;
2406 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl);
2407 if (err)
2408 return err;
2409 err = esr_read_glue0(np, i, &glue0);
2410 if (err)
2411 return err;
2426 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl);
2427 if (err)
2428 return err;
2429 err = esr_write_glue0(np, i, glue0);
2430 if (err)
2431 return err;
2464 int err;
2465 err = serdes_init_1g_serdes(np);
2466 if (!err) {
2588 int err, ignore;
2591 err = niu_xcvr_init(np);
2592 if (err)
2593 return err;
2596 err = niu_serdes_init(np);
2597 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY))
2598 return err;
2600 err = niu_xcvr_init(np);
2601 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY))
2801 int err;
2804 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2805 if (!err) {
2815 return err;
2838 int err;
2841 err = tcam_wait_bit(np, TCAM_CTL_STAT);
2842 if (!err)
2845 return err;
2979 int err;
2986 err = tcam_user_eth_class_enable(np, i, 0);
2987 if (err)
2988 return err;
2991 err = tcam_user_ip_class_enable(np, i, 0);
2992 if (err)
2993 return err;
3004 int err = tcam_flush(np, i);
3005 if (err)
3006 return err;
3114 int err = fflp_set_partition(np, 0, 0, 0, 0);
3115 if (err)
3116 return err;
3153 int err = hash_write(np, 0, i, 1, (u64 *) &ent);
3154 if (err)
3155 return err;
3164 int err;
3169 err = 0;
3174 err = fflp_disable_all_partitions(np);
3175 if (err) {
3177 "fflp_disable_all_partitions failed, err=%d\n",
3178 err);
3183 err = tcam_early_init(np);
3184 if (err) {
3186 "tcam_early_init failed, err=%d\n", err);
3194 err = tcam_flush_all(np);
3195 if (err) {
3197 "tcam_flush_all failed, err=%d\n", err);
3201 err = fflp_hash_clear(np);
3202 if (err) {
3204 "fflp_hash_clear failed, err=%d\n",
3205 err);
3216 return err;
3345 int err = niu_rbr_add_page(np, rp, mask, index);
3347 if (unlikely(err)) {
3497 int err, index = rp->rbr_index;
3499 err = 0;
3501 err = niu_rbr_add_page(np, rp, mask, index);
3502 if (unlikely(err))
3509 return err;
3817 int err = 0;
3822 err = -EINVAL;
3824 if (err) {
3835 return err;
4062 int i, err = 0;
4077 err = r;
4095 err = r;
4102 err = r;
4108 err = r;
4113 err = r;
4117 if (err)
4120 return err;
4222 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2);
4223 if (err)
4457 int i, port, err;
4471 err = -ENOMEM;
4487 err = niu_alloc_rx_ring_info(np, rp);
4488 if (err)
4504 err = niu_rbr_fill(np, rp, GFP_KERNEL);
4505 if (err)
4511 err = -ENOMEM;
4527 err = niu_alloc_tx_ring_info(np, rp);
4528 if (err)
4536 return err;
4576 int err;
4581 err = niu_tx_cs_reset_poll(np, channel);
4582 if (!err)
4585 return err;
4655 int err, channel = rp->tx_channel;
4658 err = niu_tx_channel_stop(np, channel);
4659 if (err)
4660 return err;
4662 err = niu_tx_channel_reset(np, channel);
4663 if (err)
4664 return err;
4666 err = niu_tx_channel_lpage_init(np, channel);
4667 if (err)
4668 return err;
4747 int i, err, num_alt = niu_num_alt_addr(np);
4750 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1);
4751 if (err)
4752 return err;
4754 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1);
4755 if (err)
4756 return err;
4759 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1);
4760 if (err)
4761 return err;
4908 int err, channel = rp->rx_channel;
4911 err = niu_rx_channel_reset(np, channel);
4912 if (err)
4913 return err;
4915 err = niu_rx_channel_lpage_init(np, channel);
4916 if (err)
4917 return err;
4934 err = niu_compute_rbr_cfig_b(rp, &val);
4935 if (err)
4936 return err;
4946 err = niu_enable_rx_channel(np, channel, 1);
4947 if (err)
4948 return err;
4963 int err, i;
4975 err = niu_init_hostinfo(np);
4976 if (err)
4977 return err;
4982 err = niu_init_one_rx_channel(np, rp);
4983 if (err)
4984 return err;
4995 int index, err;
5008 err = tcam_write(np, index, tp->key, tp->key_mask);
5009 if (err)
5010 return err;
5011 err = tcam_assoc_write(np, index, tp->assoc_data);
5012 if (err)
5013 return err;
5024 int i, err;
5029 err = niu_init_hostinfo(np);
5030 if (err)
5031 return err;
5043 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num,
5045 if (err)
5046 return err;
5052 err = niu_set_tcam_key(np, i, parent->tcam_key[index]);
5053 if (err)
5054 return err;
5055 err = niu_set_flow_key(np, i, parent->flow_key[index]);
5056 if (err)
5057 return err;
5060 err = niu_set_ip_frag_rule(np);
5061 if (err)
5062 return err;
5088 int err;
5090 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5092 if (err) {
5095 return err;
5103 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY,
5105 if (err) {
5108 return err;
5135 int i, max, err;
5152 err = niu_zcp_write(np, i, data);
5153 if (err)
5154 return err;
5155 err = niu_zcp_read(np, i, rbuf);
5156 if (err)
5157 return err;
5202 int i, max, err;
5226 err = niu_ipp_reset(np);
5227 if (err)
5228 return err;
5790 int err;
5793 err = niu_init_pcs(np);
5794 if (err)
5795 return err;
5797 err = niu_reset_tx_mac(np);
5798 if (err)
5799 return err;
5801 err = niu_reset_rx_mac(np);
5802 if (err)
5803 return err;
5919 int i, err;
5930 err = niu_init_one_tx_channel(np, rp);
5931 if (err)
5932 return err;
5936 err = niu_init_rx_channels(np);
5937 if (err)
5941 err = niu_init_classifier_hw(np);
5942 if (err)
5946 err = niu_init_zcp(np);
5947 if (err)
5951 err = niu_init_ipp(np);
5952 if (err)
5956 err = niu_init_mac(np);
5957 if (err)
5976 return err;
6028 int i, j, err;
6032 err = 0;
6036 err = request_irq(lp->irq, niu_interrupt, IRQF_SHARED,
6038 if (err)
6051 return err;
6084 int err;
6088 err = niu_alloc_channels(np);
6089 if (err)
6092 err = niu_enable_interrupts(np, 0);
6093 if (err)
6096 err = niu_request_irq(np);
6097 if (err)
6104 err = niu_init_hw(np);
6105 if (!err) {
6109 err = niu_enable_interrupts(np, 1);
6110 if (err)
6116 if (err) {
6137 return err;
6313 int i, alt_cnt, err;
6337 err = niu_set_alt_mac(np, index, ha->addr);
6338 if (err)
6340 err, index);
6341 err = niu_enable_alt_mac(np, index, 1);
6342 if (err)
6344 err, index);
6355 err = niu_enable_alt_mac(np, i, 0);
6356 if (err)
6358 err, i);
6432 int i, j, k, err;
6452 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k);
6453 if (unlikely(err))
6484 int err;
6508 err = niu_init_hw(np);
6509 if (!err) {
6731 int err, orig_jumbo, new_jumbo;
6748 err = niu_alloc_channels(np);
6749 if (err)
6750 return err;
6754 err = niu_init_hw(np);
6755 if (!err) {
6759 err = niu_enable_interrupts(np, 1);
6760 if (err)
6766 if (!err) {
6774 return err;
7420 int err, ret;
7548 err = tcam_write(np, idx, tp->key, tp->key_mask);
7549 if (err) {
7553 err = tcam_assoc_write(np, idx, tp->assoc_data);
7554 if (err) {
7991 int err = niu_pci_eeprom_read(np, off);
7994 if (err < 0)
7995 return err;
7996 val = (err << 8);
7997 err = niu_pci_eeprom_read(np, off + 1);
7998 if (err < 0)
7999 return err;
8000 val |= (err & 0xff);
8007 int err = niu_pci_eeprom_read(np, off);
8010 if (err < 0)
8011 return err;
8013 val = (err & 0xff);
8014 err = niu_pci_eeprom_read(np, off + 1);
8015 if (err < 0)
8016 return err;
8018 val |= (err & 0xff) << 8;
8029 int err = niu_pci_eeprom_read(np, off + i);
8030 if (err < 0)
8031 return err;
8032 *namebuf++ = err;
8033 if (!err)
8083 int len, err, prop_len;
8093 err = niu_pci_eeprom_read(np, start + 2);
8094 if (err < 0)
8095 return err;
8096 len = err;
8102 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64);
8103 if (err < 0)
8104 return err;
8140 u32 off = start + 5 + err;
8147 err = niu_pci_eeprom_read(np, off + i);
8148 if (err < 0)
8149 return err;
8150 *prop_buf++ = err;
8164 int err;
8166 err = niu_pci_eeprom_read16_swp(np, start + 1);
8167 if (err < 0)
8168 return err;
8170 offset = err + 3;
8176 err = niu_pci_eeprom_read(np, here);
8177 if (err < 0)
8178 return err;
8179 if (err != 0x90)
8182 err = niu_pci_eeprom_read16_swp(np, here + 1);
8183 if (err < 0)
8184 return err;
8187 end = start + offset + err;
8189 offset += err;
8191 err = niu_pci_vpd_scan_props(np, here, end);
8192 if (err < 0)
8193 return err;
8195 if (err == 1)
8205 int err;
8211 err = niu_pci_eeprom_read16(np, start + 0);
8212 if (err != 0x55aa)
8216 err = niu_pci_eeprom_read16(np, start + 23);
8217 if (err < 0)
8219 start += err;
8222 err = niu_pci_eeprom_read16(np, start + 0);
8223 if (err != 0x5043)
8225 err = niu_pci_eeprom_read16(np, start + 2);
8226 if (err != 0x4952)
8230 err = niu_pci_eeprom_read(np, start + 20);
8231 if (err < 0)
8233 if (err != 0x01) {
8234 err = niu_pci_eeprom_read(np, ret + 2);
8235 if (err < 0)
8238 start = ret + (err * 512);
8242 err = niu_pci_eeprom_read16_swp(np, start + 8);
8243 if (err < 0)
8244 return err;
8245 ret += err;
8247 err = niu_pci_eeprom_read(np, ret + 0);
8248 if (err != 0x82)
8751 int port, err;
8757 err = 0;
8765 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8767 if (err)
8773 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8775 if (err)
8779 err = phy_record(parent, info, dev_id_1, dev_id_2, port,
8781 if (err)
8786 return err;
8795 int err;
8826 err = fill_phy_probe_info(np, parent, info);
8827 if (err)
8828 return err;
8921 int err, i;
8924 err = walk_phys(np, parent);
8925 if (err)
8926 return err;
9078 int i, err, ldg_rotor;
9084 err = niu_n2_irq_init(np, ldg_num_map);
9085 if (err)
9086 return err;
9105 err = niu_set_ldg_sid(np, lp->ldg_num, port, i);
9106 if (err)
9107 return err;
9124 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor],
9126 if (err)
9127 return err;
9134 err = niu_ldg_assign_ldn(np, parent,
9137 if (err)
9138 return err;
9144 err = niu_ldg_assign_ldn(np, parent,
9147 if (err)
9148 return err;
9162 err = niu_ldg_assign_ldn(np, parent,
9165 if (err)
9166 return err;
9177 err = niu_ldg_assign_ldn(np, parent,
9180 if (err)
9181 return err;
9263 int err, have_props;
9266 err = niu_get_of_props(np);
9267 if (err == -ENODEV)
9268 return err;
9270 have_props = !err;
9272 err = niu_init_mac_ipp_pcs_base(np);
9273 if (err)
9274 return err;
9277 err = niu_get_and_validate_port(np);
9278 if (err)
9279 return err;
9290 err = niu_pci_vpd_fetch(np, offset);
9291 if (err < 0)
9292 return err;
9298 err = niu_get_and_validate_port(np);
9299 if (err)
9300 return err;
9304 err = niu_get_and_validate_port(np);
9305 if (err)
9306 return err;
9307 err = niu_pci_probe_sprom(np);
9308 if (err)
9309 return err;
9313 err = niu_probe_ports(np);
9314 if (err)
9315 return err;
9322 err = niu_determine_phy_disposition(np);
9323 if (!err)
9324 err = niu_init_link(np);
9326 return err;
9456 int err = device_create_file(&plat_dev->dev,
9458 if (err)
9526 int err;
9529 err = sysfs_create_link(&p->plat_dev->dev.kobj,
9532 if (!err) {
9724 int err;
9729 err = pci_enable_device(pdev);
9730 if (err) {
9732 return err;
9738 err = -ENODEV;
9742 err = pci_request_regions(pdev, DRV_MODULE_NAME);
9743 if (err) {
9750 err = -ENODEV;
9757 err = -ENOMEM;
9770 err = -ENOMEM;
9781 err = pci_set_dma_mask(pdev, dma_mask);
9782 if (!err) {
9784 err = pci_set_consistent_dma_mask(pdev, dma_mask);
9785 if (err) {
9790 if (err) {
9791 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9792 if (err) {
9805 err = -ENOMEM;
9820 err = niu_get_invariants(np);
9821 if (err) {
9822 if (err != -ENODEV)
9827 err = register_netdev(dev);
9828 if (err) {
9857 return err;
9915 int err;
9924 err = niu_init_hw(np);
9925 if (!err) {
9933 return err;
10011 int err;
10025 err = -ENOMEM;
10036 err = -ENOMEM;
10047 err = -ENOMEM;
10056 err = -ENOMEM;
10065 err = -ENOMEM;
10071 err = niu_get_invariants(np);
10072 if (err) {
10073 if (err != -ENODEV)
10078 err = register_netdev(dev);
10079 if (err) {
10116 return err;
10177 int err = 0;
10184 err = platform_driver_register(&niu_of_driver);
10187 if (!err) {
10188 err = pci_register_driver(&niu_pci_driver);
10190 if (err)
10195 return err;