Lines Matching defs:val
401 static int cas_phy_write(struct cas *cp, int reg, u16 val)
410 cmd |= val & MIF_FRAME_DATA_MASK;
734 u32 val = readl(cp->regs + REG_PCS_MII_CTRL);
737 val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN);
741 val |= PCS_MII_CTRL_DUPLEX;
742 val &= ~PCS_MII_AUTONEG_EN;
746 writel(val, cp->regs + REG_PCS_MII_CTRL);
773 u16 val;
778 val = cas_phy_read(cp, MII_BMCR);
779 if ((val & BMCR_RESET) == 0)
853 u16 val;
884 val = cas_phy_read(cp, BROADCOM_MII_REG4);
885 val = cas_phy_read(cp, BROADCOM_MII_REG4);
886 if (val & 0x0080) {
889 val & ~0x0080);
908 val = cas_phy_read(cp, MII_BMCR);
909 val &= ~BMCR_ANENABLE;
910 cas_phy_write(cp, MII_BMCR, val);
924 val = cas_phy_read(cp, CAS_MII_1000_CTRL);
925 val &= ~CAS_ADVERTISE_1000HALF;
926 val |= CAS_ADVERTISE_1000FULL;
927 cas_phy_write(cp, CAS_MII_1000_CTRL, val);
932 u32 val;
943 val = readl(cp->regs + REG_PCS_MII_CTRL);
944 val |= PCS_MII_RESET;
945 writel(val, cp->regs + REG_PCS_MII_CTRL);
964 val = readl(cp->regs + REG_PCS_MII_ADVERT);
965 val &= ~PCS_MII_ADVERT_HD;
966 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE |
968 writel(val, cp->regs + REG_PCS_MII_ADVERT);
1149 u32 val;
1156 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val);
1157 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask);
1158 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI);
1160 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10);
1161 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop);
1162 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext);
1163 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff);
1164 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext);
1165 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff);
1166 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op);
1167 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID);
1169 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask);
1170 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift);
1171 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab);
1172 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg);
1173 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW);
1182 u32 val;
1186 val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL);
1187 val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0));
1188 val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0));
1191 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1));
1192 writel(val, cp->regs + REG_RX_CFG);
1194 val = (unsigned long) cp->init_rxds[0] -
1196 writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI);
1197 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW);
1204 val = (unsigned long) cp->init_rxds[1] -
1206 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI);
1207 writel((desc_dma + val) & 0xffffffff, cp->regs +
1214 val = (unsigned long) cp->init_rxcs[0] -
1216 writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI);
1217 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW);
1222 val = (unsigned long) cp->init_rxcs[i] -
1224 writel((desc_dma + val) >> 32, cp->regs +
1226 writel((desc_dma + val) & 0xffffffff, cp->regs +
1252 val = CAS_BASE(RX_PAUSE_THRESH_OFF,
1254 val |= CAS_BASE(RX_PAUSE_THRESH_ON,
1256 writel(val, cp->regs + REG_RX_PAUSE_THRESH);
1272 val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL);
1273 val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL);
1274 writel(val, cp->regs + REG_RX_BLANK);
1284 /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */
1285 val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL);
1286 writel(val, cp->regs + REG_RX_AE_THRESH);
1288 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1));
1289 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH);
1298 val = 0;
1300 val = 0x1;
1302 val = 0x2;
1304 val = 0x3;
1321 val = CAS_BASE(RX_PAGE_SIZE, val);
1322 val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i);
1323 val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10));
1324 val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1);
1325 writel(val, cp->regs + REG_RX_PAGE_SIZE);
1331 val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS);
1332 val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK;
1333 val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL);
1334 writel(val, cp->regs + REG_HP_CFG);
1437 u32 val;
1485 val = readl(cp->regs + REG_RX_CFG);
1486 writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG);
1488 val = readl(cp->regs + REG_MAC_RX_CFG);
1489 writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG);
1555 u16 val;
1567 val = cas_phy_read(cp, MII_BMCR);
1572 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE);
1573 val |= BMCR_FULLDPLX;
1574 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ?
1576 cas_phy_write(cp, MII_BMCR, val);
1584 val = cas_phy_read(cp, MII_BMCR);
1586 if (val & CAS_BMCR_SPEED1000) { /* gigabit */
1587 val &= ~CAS_BMCR_SPEED1000;
1588 val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
1589 cas_phy_write(cp, MII_BMCR, val);
1593 if (val & BMCR_SPEED100) {
1594 if (val & BMCR_FULLDPLX) /* fd failed */
1595 val &= ~BMCR_FULLDPLX;
1597 val &= ~BMCR_SPEED100;
1599 cas_phy_write(cp, MII_BMCR, val);
2864 u32 val;
2877 val = TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 |
2887 val |= CAS_TX_RINGN_BASE(i);
2895 writel(val, cp->regs + REG_TX_CFG);
3458 u32 val;
3462 val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN;
3463 writel(val, cp->regs + REG_TX_CFG);
3464 val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN;
3465 writel(val, cp->regs + REG_RX_CFG);
3468 val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN;
3469 writel(val, cp->regs + REG_MAC_TX_CFG);
3470 val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN;
3471 writel(val, cp->regs + REG_MAC_RX_CFG);
3475 val = readl(cp->regs + REG_MAC_TX_CFG);
3476 if ((val & MAC_TX_CFG_EN))
3483 val = readl(cp->regs + REG_MAC_RX_CFG);
3484 if ((val & MAC_RX_CFG_EN)) {
3519 u32 val = readl(cp->regs + REG_PCS_MII_LPA);
3520 *fd = (val & PCS_MII_LPA_FD) ? 1 : 0;
3521 *pause = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00;
3522 if (val & PCS_MII_LPA_ASYM_PAUSE)
3531 u32 val;
3538 val = cas_phy_read(cp, MII_LPA);
3539 if (val & CAS_LPA_PAUSE)
3542 if (val & CAS_LPA_ASYM_PAUSE)
3545 if (val & LPA_DUPLEX)
3547 if (val & LPA_100)
3551 val = cas_phy_read(cp, CAS_MII_1000_STATUS);
3552 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF))
3554 if (val & CAS_LPA_1000FULL)
3566 u32 val;
3575 val = cas_phy_read(cp, MII_BMCR);
3576 if (val & BMCR_ANENABLE) {
3580 if (val & BMCR_FULLDPLX)
3583 if (val & BMCR_SPEED100)
3585 else if (val & CAS_BMCR_SPEED1000)
3592 val = readl(cp->regs + REG_PCS_MII_CTRL);
3594 if ((val & PCS_MII_AUTONEG_EN) == 0) {
3595 if (val & PCS_MII_CTRL_DUPLEX)
3603 val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED;
3605 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN;
3607 val |= MAC_XIF_DISABLE_ECHO;
3610 val |= MAC_XIF_FDPLX_LED;
3612 val |= MAC_XIF_GMII_MODE;
3613 writel(val, cp->regs + REG_MAC_XIF_CFG);
3616 val = MAC_TX_CFG_IPG_EN;
3618 val |= MAC_TX_CFG_IGNORE_CARRIER;
3619 val |= MAC_TX_CFG_IGNORE_COLL;
3622 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN;
3623 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM;
3626 /* val now set up for REG_MAC_TX_CFG */
3634 writel(val | MAC_TX_CFG_CARRIER_EXTEND,
3637 val = readl(cp->regs + REG_MAC_RX_CFG);
3638 val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */
3639 writel(val | MAC_RX_CFG_CARRIER_EXTEND,
3649 writel(val, cp->regs + REG_MAC_TX_CFG);
3654 val = readl(cp->regs + REG_MAC_RX_CFG);
3656 val |= MAC_RX_CFG_STRIP_FCS;
3660 val &= ~MAC_RX_CFG_STRIP_FCS;
3664 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND,
3682 val = readl(cp->regs + REG_MAC_CTRL_CFG);
3683 val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN);
3685 val |= MAC_CTRL_CFG_SEND_PAUSE_EN;
3687 val |= MAC_CTRL_CFG_RECV_PAUSE_EN;
3690 writel(val, cp->regs + REG_MAC_CTRL_CFG);
3749 u32 val = readl(cp->regs + REG_SW_RESET);
3750 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0)
3778 u32 val;
3786 val = readl(cp->regs + REG_TX_CFG);
3787 val &= ~TX_CFG_DMA_EN;
3788 writel(val, cp->regs + REG_TX_CFG);
3790 val = readl(cp->regs + REG_RX_CFG);
3791 val &= ~RX_CFG_DMA_EN;
3792 writel(val, cp->regs + REG_RX_CFG);
4133 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE);
4135 int tlm = CAS_VAL(MAC_SM_TLM, val);
4138 (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) {
4140 "tx err: MAC_STATE[%08x]\n", val);
4145 val = readl(cp->regs + REG_TX_FIFO_PKT_CNT);
4148 if ((val == 0) && (wptr != rptr)) {
4151 val, wptr, rptr);
4374 u32 val;
4378 val = hval;
4380 val= readl(cp->regs+ethtool_register_table[i].offsets);
4382 memcpy(p, (u8 *)&val, sizeof(u32));
4795 u32 val;
4808 pci_read_config_dword(pdev, 0x40, &val);
4809 val &= ~0x00040000;
4810 pci_write_config_dword(pdev, 0x40, val);