Lines Matching defs:stat
982 u32 stat, state_machine;
989 stat = readl(cp->regs + REG_PCS_MII_STATUS);
990 if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0)
991 stat = readl(cp->regs + REG_PCS_MII_STATUS);
996 if ((stat & (PCS_MII_STATUS_AUTONEG_COMP |
1006 stat &= ~PCS_MII_STATUS_LINK_STATUS;
1008 stat |= PCS_MII_STATUS_LINK_STATUS;
1011 if (stat & PCS_MII_STATUS_LINK_STATUS) {
1059 stat = readl(cp->regs + REG_PCS_SERDES_STATE);
1060 if (stat == 0x03)
1087 u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS);
1089 if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0)
1497 u32 stat = readl(cp->regs + REG_MAC_RX_STATUS);
1499 if (!stat)
1502 netif_dbg(cp, intr, cp->dev, "rxmac interrupt, stat: 0x%x\n", stat);
1506 if (stat & MAC_RX_ALIGN_ERR)
1509 if (stat & MAC_RX_CRC_ERR)
1512 if (stat & MAC_RX_LEN_ERR)
1515 if (stat & MAC_RX_OVERFLOW) {
1530 u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS);
1532 if (!stat)
1536 "mac interrupt, stat: 0x%x\n", stat);
1542 if (stat & MAC_CTRL_PAUSE_STATE)
1545 if (stat & MAC_CTRL_PAUSE_RECEIVED)
1546 cp->pause_last_time_recvd = (stat >> 16);
1669 u32 stat = readl(cp->regs + REG_MIF_STATUS);
1673 if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0)
1676 bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat);
1683 u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS);
1685 if (!stat)
1689 stat, readl(cp->regs + REG_BIM_DIAG));
1692 if ((stat & PCI_ERR_BADACK) &&
1696 if (stat & PCI_ERR_DTRTO)
1698 if (stat & PCI_ERR_OTHER)
1700 if (stat & PCI_ERR_BIM_DMA_WRITE)
1702 if (stat & PCI_ERR_BIM_DMA_READ)
1706 if (stat & PCI_ERR_OTHER) {