Lines Matching refs:val
307 u32 val;
310 val = readl(ioaddr + MTL_OPERATION_MODE);
311 val &= ~MTL_FRPE;
312 writel(val, ioaddr + MTL_OPERATION_MODE);
314 ret = readl_poll_timeout(ioaddr + MTL_RXP_CONTROL_STATUS, val,
315 val & RXPI, 1, 10000);
323 u32 val;
325 val = readl(ioaddr + MTL_OPERATION_MODE);
326 val |= MTL_FRPE;
327 writel(val, ioaddr + MTL_OPERATION_MODE);
336 for (i = 0; i < (sizeof(entry->val) / sizeof(u32)); i++) {
337 int real_pos = pos * (sizeof(entry->val) / sizeof(u32)) + i;
338 u32 val;
342 val, !(val & STARTBUSY), 1, 10000);
347 val = *((u32 *)&entry->val + i);
348 writel(val, ioaddr + MTL_RXP_IACC_DATA);
351 val = real_pos & ADDR;
352 writel(val, ioaddr + MTL_RXP_IACC_CTRL_STATUS);
355 val |= WRRDN;
356 writel(val, ioaddr + MTL_RXP_IACC_CTRL_STATUS);
359 val |= STARTBUSY;
360 writel(val, ioaddr + MTL_RXP_IACC_CTRL_STATUS);
364 val, !(val & STARTBUSY), 1, 10000);
418 u32 old_val, val;
422 val = old_val & ~GMAC_CONFIG_RE;
423 writel(val, ioaddr + GMAC_CONFIG);
447 entry->val.af = 0;
448 entry->val.rf = 0;
449 entry->val.nc = 1;
450 entry->val.ok_index = nve + 2;
486 val = (nve << 16) & NPE;
487 val |= nve & NVE;
488 writel(val, ioaddr + MTL_RXP_CONTROL_STATUS);
504 u32 val = readl(ioaddr + MAC_PPS_CONTROL);
514 val &= ~PPSx_MASK(index);
517 val |= PPSCMDx(index, 0x5);
518 val |= PPSEN0;
519 writel(val, ioaddr + MAC_PPS_CONTROL);
523 val |= TRGTMODSELx(index, 0x2);
524 val |= PPSEN0;
525 writel(val, ioaddr + MAC_PPS_CONTROL);
550 val |= PPSCMDx(index, 0x2);
551 writel(val, ioaddr + MAC_PPS_CONTROL);
555 static int dwmac5_est_write(void __iomem *ioaddr, u32 reg, u32 val, bool gcl)
559 writel(val, ioaddr + MTL_EST_GCL_DATA);