Lines Matching defs:value
21 static void dwmac5_log_error(struct net_device *ndev, u32 value, bool corr,
31 mask = value;
81 u32 value;
83 value = readl(ioaddr + MAC_DPP_FSM_INT_STATUS);
84 writel(value, ioaddr + MAC_DPP_FSM_INT_STATUS);
86 dwmac5_log_error(ndev, value, correctable, "MAC", dwmac5_mac_errors,
129 u32 value;
131 value = readl(ioaddr + MTL_ECC_INT_STATUS);
132 writel(value, ioaddr + MTL_ECC_INT_STATUS);
134 dwmac5_log_error(ndev, value, correctable, "MTL", dwmac5_mtl_errors,
177 u32 value;
179 value = readl(ioaddr + DMA_ECC_INT_STATUS);
180 writel(value, ioaddr + DMA_ECC_INT_STATUS);
182 dwmac5_log_error(ndev, value, correctable, "DMA", dwmac5_dma_errors,
188 u32 value;
194 value = readl(ioaddr + MTL_ECC_CONTROL);
195 value |= TSOEE; /* TSO ECC */
196 value |= MRXPEE; /* MTL RX Parser ECC */
197 value |= MESTEE; /* MTL EST ECC */
198 value |= MRXEE; /* MTL RX FIFO ECC */
199 value |= MTXEE; /* MTL TX FIFO ECC */
200 writel(value, ioaddr + MTL_ECC_CONTROL);
203 value = readl(ioaddr + MTL_ECC_INT_ENABLE);
204 value |= RPCEIE; /* RX Parser Memory Correctable Error */
205 value |= ECEIE; /* EST Memory Correctable Error */
206 value |= RXCEIE; /* RX Memory Correctable Error */
207 value |= TXCEIE; /* TX Memory Correctable Error */
208 writel(value, ioaddr + MTL_ECC_INT_ENABLE);
211 value = readl(ioaddr + DMA_ECC_INT_ENABLE);
212 value |= TCEIE; /* TSO Memory Correctable Error */
213 writel(value, ioaddr + DMA_ECC_INT_ENABLE);
220 value = readl(ioaddr + MAC_FSM_CONTROL);
221 value |= PRTYEN; /* FSM Parity Feature */
222 value |= TMOUTEN; /* FSM Timeout Feature */
223 writel(value, ioaddr + MAC_FSM_CONTROL);
226 value = readl(ioaddr + MTL_DPP_CONTROL);
227 value |= EDPP;
228 writel(value, ioaddr + MTL_DPP_CONTROL);
237 value |= EPSI;
238 writel(value, ioaddr + MTL_DPP_CONTROL);
609 u32 value;
612 value = readl(ioaddr + MAC_FPE_CTRL_STS);
614 value &= ~EFPE;
616 writel(value, ioaddr + MAC_FPE_CTRL_STS);
620 value = readl(ioaddr + GMAC_RXQ_CTRL1);
621 value &= ~GMAC_RXQCTRL_FPRQ;
622 value |= (num_rxq - 1) << GMAC_RXQCTRL_FPRQ_SHIFT;
623 writel(value, ioaddr + GMAC_RXQ_CTRL1);
625 value = readl(ioaddr + MAC_FPE_CTRL_STS);
626 value |= EFPE;
627 writel(value, ioaddr + MAC_FPE_CTRL_STS);