Lines Matching refs:val
66 u32 val;
73 val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG);
74 val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK;
78 val |= EMAC_SPLITTER_CTRL_SPEED_1000;
81 val |= EMAC_SPLITTER_CTRL_SPEED_100;
84 val |= EMAC_SPLITTER_CTRL_SPEED_10;
89 writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG);
238 static int socfpga_set_phy_mode_common(int phymode, u32 *val)
245 *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
250 *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
253 *val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
267 u32 ctrl, val, module;
269 if (socfpga_set_phy_mode_common(phymode, &val)) {
274 /* Overwrite val to GMII if splitter core is enabled. The phymode here
279 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
287 ctrl |= val << reg_shift;
329 u32 ctrl, val, module;
331 if (socfpga_set_phy_mode_common(phymode, &val))
334 /* Overwrite val to GMII if splitter core is enabled. The phymode here
339 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
347 ctrl |= val;