Lines Matching refs:ethqos
95 static int rgmii_readl(struct qcom_ethqos *ethqos, unsigned int offset)
97 return readl(ethqos->rgmii_base + offset);
100 static void rgmii_writel(struct qcom_ethqos *ethqos,
103 writel(value, ethqos->rgmii_base + offset);
106 static void rgmii_updatel(struct qcom_ethqos *ethqos,
111 temp = rgmii_readl(ethqos, offset);
113 rgmii_writel(ethqos, temp, offset);
116 static void rgmii_dump(struct qcom_ethqos *ethqos)
118 dev_dbg(ðqos->pdev->dev, "Rgmii register dump\n");
119 dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_CONFIG: %x\n",
120 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG));
121 dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG: %x\n",
122 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG));
123 dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DDR_CONFIG: %x\n",
124 rgmii_readl(ethqos, SDCC_HC_REG_DDR_CONFIG));
125 dev_dbg(ðqos->pdev->dev, "SDCC_HC_REG_DLL_CONFIG2: %x\n",
126 rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG2));
127 dev_dbg(ðqos->pdev->dev, "SDC4_STATUS: %x\n",
128 rgmii_readl(ethqos, SDC4_STATUS));
129 dev_dbg(ðqos->pdev->dev, "SDCC_USR_CTL: %x\n",
130 rgmii_readl(ethqos, SDCC_USR_CTL));
131 dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_CONFIG2: %x\n",
132 rgmii_readl(ethqos, RGMII_IO_MACRO_CONFIG2));
133 dev_dbg(ðqos->pdev->dev, "RGMII_IO_MACRO_DEBUG1: %x\n",
134 rgmii_readl(ethqos, RGMII_IO_MACRO_DEBUG1));
135 dev_dbg(ðqos->pdev->dev, "EMAC_SYSTEM_LOW_POWER_DEBUG: %x\n",
136 rgmii_readl(ethqos, EMAC_SYSTEM_LOW_POWER_DEBUG));
145 ethqos_update_rgmii_clk(struct qcom_ethqos *ethqos, unsigned int speed)
149 ethqos->rgmii_clk_rate = RGMII_1000_NOM_CLK_FREQ;
153 ethqos->rgmii_clk_rate = RGMII_ID_MODE_100_LOW_SVS_CLK_FREQ;
157 ethqos->rgmii_clk_rate = RGMII_ID_MODE_10_LOW_SVS_CLK_FREQ;
161 clk_set_rate(ethqos->rgmii_clk, ethqos->rgmii_clk_rate);
164 static void ethqos_set_func_clk_en(struct qcom_ethqos *ethqos)
166 rgmii_updatel(ethqos, RGMII_CONFIG_FUNC_CLK_EN,
184 static int ethqos_dll_configure(struct qcom_ethqos *ethqos)
190 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EN,
194 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CDR_EXT_EN,
198 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
202 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
205 rgmii_updatel(ethqos, SDCC_DLL_MCLK_GATING_EN,
208 rgmii_updatel(ethqos, SDCC_DLL_CDR_FINE_PHASE,
213 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
221 dev_err(ðqos->pdev->dev, "Clear CK_OUT_EN timedout\n");
224 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
230 val = rgmii_readl(ethqos, SDCC_HC_REG_DLL_CONFIG);
238 dev_err(ðqos->pdev->dev, "Set CK_OUT_EN timedout\n");
241 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_CAL_EN,
244 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DLL_CLOCK_DIS,
247 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_MCLK_FREQ_CALC,
250 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SEL,
253 rgmii_updatel(ethqos, SDCC_DLL_CONFIG2_DDR_TRAFFIC_INIT_SW,
260 static int ethqos_rgmii_macro_init(struct qcom_ethqos *ethqos)
263 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_TO_RX_LOOPBACK_EN,
267 rgmii_updatel(ethqos, RGMII_CONFIG_INTF_SEL,
270 switch (ethqos->speed) {
272 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
274 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
276 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
279 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
281 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
283 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
286 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
288 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
293 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_RCLK_DLY,
295 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_PRG_DLY_EN,
298 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
303 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
305 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
308 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
310 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
312 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
314 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
317 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_2,
319 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
321 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
324 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
326 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
329 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
332 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
337 rgmii_updatel(ethqos, RGMII_CONFIG_DDR_MODE,
339 rgmii_updatel(ethqos, RGMII_CONFIG_BYPASS_TX_ID_EN,
342 rgmii_updatel(ethqos, RGMII_CONFIG_POS_NEG_DATA_SEL,
344 rgmii_updatel(ethqos, RGMII_CONFIG_PROG_SWAP,
346 rgmii_updatel(ethqos, RGMII_CONFIG2_DATA_DIVIDE_CLK_SEL,
348 rgmii_updatel(ethqos, RGMII_CONFIG2_TX_CLK_PHASE_SHIFT_EN,
350 rgmii_updatel(ethqos, RGMII_CONFIG_MAX_SPD_PRG_9,
353 rgmii_updatel(ethqos, RGMII_CONFIG2_RSVD_CONFIG15,
355 rgmii_updatel(ethqos, RGMII_CONFIG2_RX_PROG_SWAP,
358 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_CODE,
360 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY,
363 rgmii_updatel(ethqos, SDCC_DDR_CONFIG_EXT_PRG_RCLK_DLY_EN,
366 rgmii_updatel(ethqos, RGMII_CONFIG_LOOPBACK_EN,
370 dev_err(ðqos->pdev->dev,
371 "Invalid speed %d\n", ethqos->speed);
378 static int ethqos_configure(struct qcom_ethqos *ethqos)
384 for (i = 0; i < ethqos->num_por; i++)
385 rgmii_writel(ethqos, ethqos->por[i].value,
386 ethqos->por[i].offset);
387 ethqos_set_func_clk_en(ethqos);
392 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST,
396 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN,
400 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_RST, 0,
404 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_PDN, 0,
407 if (ethqos->speed != SPEED_100 && ethqos->speed != SPEED_10) {
409 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_DLL_EN,
413 rgmii_updatel(ethqos, SDCC_DLL_CONFIG_CK_OUT_EN,
418 rgmii_updatel(ethqos, GENMASK(26, 24), BIT(26), SDCC_USR_CTL);
423 dll_lock = rgmii_readl(ethqos, SDC4_STATUS);
429 dev_err(ðqos->pdev->dev,
433 if (ethqos->speed == SPEED_1000)
434 ethqos_dll_configure(ethqos);
436 ethqos_rgmii_macro_init(ethqos);
443 struct qcom_ethqos *ethqos = priv;
445 ethqos->speed = speed;
446 ethqos_update_rgmii_clk(ethqos, speed);
447 ethqos_configure(ethqos);
456 struct qcom_ethqos *ethqos;
470 ethqos = devm_kzalloc(&pdev->dev, sizeof(*ethqos), GFP_KERNEL);
471 if (!ethqos) {
476 ethqos->pdev = pdev;
478 ethqos->rgmii_base = devm_ioremap_resource(&pdev->dev, res);
479 if (IS_ERR(ethqos->rgmii_base)) {
481 ret = PTR_ERR(ethqos->rgmii_base);
486 ethqos->por = data->por;
487 ethqos->num_por = data->num_por;
489 ethqos->rgmii_clk = devm_clk_get(&pdev->dev, "rgmii");
490 if (IS_ERR(ethqos->rgmii_clk)) {
491 ret = PTR_ERR(ethqos->rgmii_clk);
495 ret = clk_prepare_enable(ethqos->rgmii_clk);
499 ethqos->speed = SPEED_1000;
500 ethqos_update_rgmii_clk(ethqos, SPEED_1000);
501 ethqos_set_func_clk_en(ethqos);
503 plat_dat->bsp_priv = ethqos;
508 if (of_device_is_compatible(np, "qcom,qcs404-ethqos"))
515 rgmii_dump(ethqos);
520 clk_disable_unprepare(ethqos->rgmii_clk);
530 struct qcom_ethqos *ethqos;
533 ethqos = get_stmmac_bsp_priv(&pdev->dev);
534 if (!ethqos)
538 clk_disable_unprepare(ethqos->rgmii_clk);
544 { .compatible = "qcom,qcs404-ethqos", .data = &emac_v2_3_0_data},
553 .name = "qcom-ethqos",