Lines Matching defs:dwmac
74 int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
96 static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg,
101 data = readl(dwmac->regs + reg);
105 writel(data, dwmac->regs + reg);
108 static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac,
118 snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev),
129 return devm_clk_register(dwmac->dev, hw);
132 static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
135 struct device *dev = dwmac->dev;
156 clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0;
160 clk = meson8b_dwmac_register_clk(dwmac, "m250_sel", mux_parents,
167 clk_configs->m250_div.reg = dwmac->regs + PRG_ETH0;
173 clk = meson8b_dwmac_register_clk(dwmac, "m250_div", &parent_data, 1,
182 clk = meson8b_dwmac_register_clk(dwmac, "fixed_div2", &parent_data, 1,
189 clk_configs->rgmii_tx_en.reg = dwmac->regs + PRG_ETH0;
191 clk = meson8b_dwmac_register_clk(dwmac, "rgmii_tx_en", &parent_data, 1,
197 dwmac->rgmii_tx_clk = clk;
202 static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac)
204 switch (dwmac->phy_mode) {
210 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
216 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
220 dev_err(dwmac->dev, "fail to set phy-mode %s\n",
221 phy_modes(dwmac->phy_mode));
228 static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac)
230 switch (dwmac->phy_mode) {
236 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
242 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
247 dev_err(dwmac->dev, "fail to set phy-mode %s\n",
248 phy_modes(dwmac->phy_mode));
255 static int meson8b_devm_clk_prepare_enable(struct meson8b_dwmac *dwmac,
264 return devm_add_action_or_reset(dwmac->dev,
269 static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
275 dwmac->tx_delay_ns >> 1);
277 if (dwmac->rx_delay_ns == 2)
282 switch (dwmac->phy_mode) {
297 dev_err(dwmac->dev, "unsupported phy-mode %s\n",
298 phy_modes(dwmac->phy_mode));
303 if (!dwmac->timing_adj_clk) {
304 dev_err(dwmac->dev,
310 ret = meson8b_devm_clk_prepare_enable(dwmac,
311 dwmac->timing_adj_clk);
313 dev_err(dwmac->dev,
319 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK |
324 if (phy_interface_mode_is_rgmii(dwmac->phy_mode)) {
326 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
334 ret = clk_set_rate(dwmac->rgmii_tx_clk, 125 * 1000 * 1000);
336 dev_err(dwmac->dev,
341 ret = meson8b_devm_clk_prepare_enable(dwmac,
342 dwmac->rgmii_tx_clk);
344 dev_err(dwmac->dev,
350 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
356 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK,
366 struct meson8b_dwmac *dwmac;
377 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
378 if (!dwmac) {
383 dwmac->data = (const struct meson8b_dwmac_data *)
385 if (!dwmac->data) {
389 dwmac->regs = devm_platform_ioremap_resource(pdev, 1);
390 if (IS_ERR(dwmac->regs)) {
391 ret = PTR_ERR(dwmac->regs);
395 dwmac->dev = &pdev->dev;
396 ret = of_get_phy_mode(pdev->dev.of_node, &dwmac->phy_mode);
404 &dwmac->tx_delay_ns))
405 dwmac->tx_delay_ns = 2;
409 &dwmac->rx_delay_ns))
410 dwmac->rx_delay_ns = 0;
412 if (dwmac->rx_delay_ns != 0 && dwmac->rx_delay_ns != 2) {
419 dwmac->timing_adj_clk = devm_clk_get_optional(dwmac->dev,
421 if (IS_ERR(dwmac->timing_adj_clk)) {
422 ret = PTR_ERR(dwmac->timing_adj_clk);
426 ret = meson8b_init_rgmii_tx_clk(dwmac);
430 ret = dwmac->data->set_phy_mode(dwmac);
434 ret = meson8b_init_prg_eth(dwmac);
438 plat_dat->bsp_priv = dwmac;
462 .compatible = "amlogic,meson8b-dwmac",
466 .compatible = "amlogic,meson8m2-dwmac",
470 .compatible = "amlogic,meson-gxbb-dwmac",
474 .compatible = "amlogic,meson-axg-dwmac",
478 .compatible = "amlogic,meson-g12a-dwmac",
489 .name = "meson8b-dwmac",