Lines Matching refs:plat
64 int (*dwmac_set_phy_interface)(struct mediatek_dwmac_plat_data *plat);
65 int (*dwmac_set_delay)(struct mediatek_dwmac_plat_data *plat);
81 static int mt2712_set_interface(struct mediatek_dwmac_plat_data *plat)
83 int rmii_clk_from_mac = plat->rmii_clk_from_mac ? RMII_CLK_SRC_INTERNAL : 0;
84 int rmii_rxc = plat->rmii_rxc ? RMII_CLK_SRC_RXC : 0;
91 * configured, equals to (plat->variant->num_clks - 1) in default for all the case,
94 plat->num_clks_to_config = plat->variant->num_clks - 1;
97 switch (plat->phy_mode) {
102 if (plat->rmii_clk_from_mac)
103 plat->num_clks_to_config++;
113 dev_err(plat->dev, "phy interface not supported\n");
117 regmap_write(plat->peri_regmap, PERI_ETH_PHY_INTF_SEL, intf_val);
122 static void mt2712_delay_ps2stage(struct mediatek_dwmac_plat_data *plat)
124 struct mac_delay_struct *mac_delay = &plat->mac_delay;
126 switch (plat->phy_mode) {
142 dev_err(plat->dev, "phy interface not supported\n");
147 static void mt2712_delay_stage2ps(struct mediatek_dwmac_plat_data *plat)
149 struct mac_delay_struct *mac_delay = &plat->mac_delay;
151 switch (plat->phy_mode) {
167 dev_err(plat->dev, "phy interface not supported\n");
172 static int mt2712_set_delay(struct mediatek_dwmac_plat_data *plat)
174 struct mac_delay_struct *mac_delay = &plat->mac_delay;
177 mt2712_delay_ps2stage(plat);
179 switch (plat->phy_mode) {
190 if (plat->rmii_clk_from_mac) {
210 if (plat->rmii_rxc) {
250 dev_err(plat->dev, "phy interface not supported\n");
253 regmap_write(plat->peri_regmap, PERI_ETH_DLY, delay_val);
254 regmap_write(plat->peri_regmap, PERI_ETH_DLY_FINE, fine_val);
256 mt2712_delay_stage2ps(plat);
271 static int mediatek_dwmac_config_dt(struct mediatek_dwmac_plat_data *plat)
273 struct mac_delay_struct *mac_delay = &plat->mac_delay;
277 plat->peri_regmap = syscon_regmap_lookup_by_phandle(plat->np, "mediatek,pericfg");
278 if (IS_ERR(plat->peri_regmap)) {
279 dev_err(plat->dev, "Failed to get pericfg syscon\n");
280 return PTR_ERR(plat->peri_regmap);
283 err = of_get_phy_mode(plat->np, &plat->phy_mode);
285 dev_err(plat->dev, "not find phy-mode\n");
289 if (!of_property_read_u32(plat->np, "mediatek,tx-delay-ps", &tx_delay_ps)) {
290 if (tx_delay_ps < plat->variant->tx_delay_max) {
293 dev_err(plat->dev, "Invalid TX clock delay: %dps\n", tx_delay_ps);
298 if (!of_property_read_u32(plat->np, "mediatek,rx-delay-ps", &rx_delay_ps)) {
299 if (rx_delay_ps < plat->variant->rx_delay_max) {
302 dev_err(plat->dev, "Invalid RX clock delay: %dps\n", rx_delay_ps);
307 mac_delay->tx_inv = of_property_read_bool(plat->np, "mediatek,txc-inverse");
308 mac_delay->rx_inv = of_property_read_bool(plat->np, "mediatek,rxc-inverse");
309 plat->rmii_rxc = of_property_read_bool(plat->np, "mediatek,rmii-rxc");
310 plat->rmii_clk_from_mac = of_property_read_bool(plat->np, "mediatek,rmii-clk-from-mac");
315 static int mediatek_dwmac_clk_init(struct mediatek_dwmac_plat_data *plat)
317 const struct mediatek_dwmac_variant *variant = plat->variant;
320 plat->clks = devm_kcalloc(plat->dev, num, sizeof(*plat->clks), GFP_KERNEL);
321 if (!plat->clks)
325 plat->clks[i].id = variant->clk_list[i];
327 plat->num_clks_to_config = variant->num_clks;
329 return devm_clk_bulk_get(plat->dev, num, plat->clks);
334 struct mediatek_dwmac_plat_data *plat = priv;
335 const struct mediatek_dwmac_variant *variant = plat->variant;
338 ret = dma_set_mask_and_coherent(plat->dev, DMA_BIT_MASK(variant->dma_bit_mask));
340 dev_err(plat->dev, "No suitable DMA available, err = %d\n", ret);
344 ret = variant->dwmac_set_phy_interface(plat);
346 dev_err(plat->dev, "failed to set phy interface, err = %d\n", ret);
350 ret = variant->dwmac_set_delay(plat);
352 dev_err(plat->dev, "failed to set delay value, err = %d\n", ret);
356 ret = clk_bulk_prepare_enable(plat->num_clks_to_config, plat->clks);
358 dev_err(plat->dev, "failed to enable clks, err = %d\n", ret);
370 struct mediatek_dwmac_plat_data *plat = priv;
372 clk_bulk_disable_unprepare(plat->num_clks_to_config, plat->clks);