Lines Matching refs:plat
13 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
17 struct plat_stmmacenet_data *plat)
19 plat->bus_id = (pci_domain_nr(pdev->bus) << 16) | PCI_DEVID(pdev->bus->number, pdev->devfn);
20 plat->interface = PHY_INTERFACE_MODE_GMII;
22 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
23 plat->has_gmac = 1;
24 plat->force_sf_dma_mode = 1;
27 plat->multicast_filter_bins = 256;
30 plat->unicast_filter_entries = 1;
33 plat->maxmtu = JUMBO_LEN;
36 plat->tx_queues_to_use = 1;
37 plat->rx_queues_to_use = 1;
40 plat->tx_queues_cfg[0].use_prio = false;
41 plat->rx_queues_cfg[0].use_prio = false;
44 plat->rx_queues_cfg[0].pkt_route = 0x0;
46 plat->dma_cfg->pbl = 32;
47 plat->dma_cfg->pblx8 = true;
49 plat->clk_ref_rate = 125000000;
50 plat->clk_ptp_rate = 125000000;
54 struct plat_stmmacenet_data *plat)
56 common_default_data(pdev, plat);
58 plat->mdio_bus_data->phy_mask = 0;
60 plat->phy_addr = -1;
61 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
85 struct plat_stmmacenet_data *plat)
87 common_default_data(pdev, plat);
89 plat->mdio_bus_data->phy_mask = 0xfffffffb;
91 plat->phy_addr = 2;
92 plat->phy_interface = PHY_INTERFACE_MODE_GMII;
95 plat->fix_mac_speed = loongson_gnet_fix_speed;
98 plat->bsp_priv = &(pdev->dev.driver_data);
110 struct plat_stmmacenet_data *plat;
123 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
124 if (!plat)
127 if (plat->mdio_node) {
132 plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
133 sizeof(*plat->mdio_bus_data),
135 if (!plat->mdio_bus_data)
139 plat->mdio_bus_data->needs_reset = true;
141 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), GFP_KERNEL);
142 if (!plat->dma_cfg)
165 ret = info->setup(pdev, plat);
172 plat->bus_id = bus_id;
179 plat->phy_interface = phy_mode;
210 return stmmac_dvr_probe(&pdev->dev, plat, &res);