Lines Matching refs:plat
32 int (*setup)(struct pci_dev *pdev, struct plat_stmmacenet_data *plat);
204 static void common_default_data(struct plat_stmmacenet_data *plat)
206 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */
207 plat->has_gmac = 1;
208 plat->force_sf_dma_mode = 1;
210 plat->mdio_bus_data->needs_reset = true;
213 plat->multicast_filter_bins = HASH_TABLE_SIZE;
216 plat->unicast_filter_entries = 1;
219 plat->maxmtu = JUMBO_LEN;
222 plat->tx_queues_to_use = 1;
223 plat->rx_queues_to_use = 1;
226 plat->tx_queues_cfg[0].use_prio = false;
227 plat->rx_queues_cfg[0].use_prio = false;
230 plat->rx_queues_cfg[0].pkt_route = 0x0;
234 struct plat_stmmacenet_data *plat)
240 plat->phy_addr = -1;
241 plat->clk_csr = 5;
242 plat->has_gmac = 0;
243 plat->has_gmac4 = 1;
244 plat->force_sf_dma_mode = 0;
245 plat->tso_en = 1;
246 plat->sph_disable = 1;
248 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP;
250 for (i = 0; i < plat->rx_queues_to_use; i++) {
251 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
252 plat->rx_queues_cfg[i].chan = i;
255 plat->rx_queues_cfg[i].use_prio = false;
258 plat->rx_queues_cfg[i].pkt_route = 0x0;
261 for (i = 0; i < plat->tx_queues_to_use; i++) {
262 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB;
265 plat->tx_queues_cfg[i].use_prio = false;
269 plat->tx_fifo_size = plat->tx_queues_to_use * 4096;
270 plat->rx_fifo_size = plat->rx_queues_to_use * 4096;
272 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR;
273 plat->tx_queues_cfg[0].weight = 0x09;
274 plat->tx_queues_cfg[1].weight = 0x0A;
275 plat->tx_queues_cfg[2].weight = 0x0B;
276 plat->tx_queues_cfg[3].weight = 0x0C;
277 plat->tx_queues_cfg[4].weight = 0x0D;
278 plat->tx_queues_cfg[5].weight = 0x0E;
279 plat->tx_queues_cfg[6].weight = 0x0F;
280 plat->tx_queues_cfg[7].weight = 0x10;
282 plat->dma_cfg->pbl = 32;
283 plat->dma_cfg->pblx8 = true;
284 plat->dma_cfg->fixed_burst = 0;
285 plat->dma_cfg->mixed_burst = 0;
286 plat->dma_cfg->aal = 0;
288 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi),
290 if (!plat->axi)
293 plat->axi->axi_lpi_en = 0;
294 plat->axi->axi_xit_frm = 0;
295 plat->axi->axi_wr_osr_lmt = 1;
296 plat->axi->axi_rd_osr_lmt = 1;
297 plat->axi->axi_blen[0] = 4;
298 plat->axi->axi_blen[1] = 8;
299 plat->axi->axi_blen[2] = 16;
301 plat->ptp_max_adj = plat->clk_ptp_rate;
302 plat->eee_usecs_rate = plat->clk_ptp_rate;
307 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev,
309 plat->clk_ptp_rate);
311 if (IS_ERR(plat->stmmac_clk)) {
313 plat->stmmac_clk = NULL;
316 ret = clk_prepare_enable(plat->stmmac_clk);
318 clk_unregister_fixed_rate(plat->stmmac_clk);
323 plat->multicast_filter_bins = HASH_TABLE_SIZE;
326 plat->unicast_filter_entries = 1;
329 plat->maxmtu = JUMBO_LEN;
331 plat->vlan_fail_q_en = true;
334 plat->vlan_fail_q = plat->rx_queues_to_use - 1;
340 struct plat_stmmacenet_data *plat)
342 plat->rx_queues_to_use = 8;
343 plat->tx_queues_to_use = 8;
344 plat->clk_ptp_rate = 200000000;
346 return intel_mgbe_common_data(pdev, plat);
350 struct plat_stmmacenet_data *plat)
352 plat->bus_id = 1;
353 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
355 plat->serdes_powerup = intel_serdes_powerup;
356 plat->serdes_powerdown = intel_serdes_powerdown;
358 return ehl_common_data(pdev, plat);
366 struct plat_stmmacenet_data *plat)
368 plat->bus_id = 1;
369 plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
371 return ehl_common_data(pdev, plat);
379 struct plat_stmmacenet_data *plat)
381 plat->bus_id = 2;
382 plat->addr64 = 32;
383 return ehl_common_data(pdev, plat);
387 struct plat_stmmacenet_data *plat)
389 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
390 return ehl_pse0_common_data(pdev, plat);
398 struct plat_stmmacenet_data *plat)
400 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
401 plat->serdes_powerup = intel_serdes_powerup;
402 plat->serdes_powerdown = intel_serdes_powerdown;
403 return ehl_pse0_common_data(pdev, plat);
411 struct plat_stmmacenet_data *plat)
413 plat->bus_id = 3;
414 plat->addr64 = 32;
415 return ehl_common_data(pdev, plat);
419 struct plat_stmmacenet_data *plat)
421 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
422 return ehl_pse1_common_data(pdev, plat);
430 struct plat_stmmacenet_data *plat)
432 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
433 plat->serdes_powerup = intel_serdes_powerup;
434 plat->serdes_powerdown = intel_serdes_powerdown;
435 return ehl_pse1_common_data(pdev, plat);
443 struct plat_stmmacenet_data *plat)
445 plat->rx_queues_to_use = 6;
446 plat->tx_queues_to_use = 4;
447 plat->clk_ptp_rate = 200000000;
449 return intel_mgbe_common_data(pdev, plat);
453 struct plat_stmmacenet_data *plat)
455 plat->bus_id = 1;
456 plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
457 plat->serdes_powerup = intel_serdes_powerup;
458 plat->serdes_powerdown = intel_serdes_powerdown;
459 return tgl_common_data(pdev, plat);
530 struct plat_stmmacenet_data *plat)
535 common_default_data(plat);
553 plat->bus_id = pci_dev_id(pdev);
554 plat->phy_addr = ret;
555 plat->phy_interface = PHY_INTERFACE_MODE_RMII;
557 plat->dma_cfg->pbl = 16;
558 plat->dma_cfg->pblx8 = true;
559 plat->dma_cfg->fixed_burst = 1;
586 struct plat_stmmacenet_data *plat;
594 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL);
595 if (!plat)
598 plat->mdio_bus_data = devm_kzalloc(&pdev->dev,
599 sizeof(*plat->mdio_bus_data),
601 if (!plat->mdio_bus_data)
604 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg),
606 if (!plat->dma_cfg)
623 plat->bsp_priv = intel_priv;
626 ret = info->setup(pdev, plat);
639 if (plat->eee_usecs_rate > 0) {
642 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1;
646 ret = stmmac_dvr_probe(&pdev->dev, plat, &res);
649 clk_disable_unprepare(plat->stmmac_clk);
650 clk_unregister_fixed_rate(plat->stmmac_clk);
672 clk_disable_unprepare(priv->plat->stmmac_clk);
673 clk_unregister_fixed_rate(priv->plat->stmmac_clk);