Lines Matching refs:netsec_write
331 static void netsec_write(struct netsec_priv *priv, u32 reg_addr, u32 val)
385 netsec_write(priv, MAC_REG_DATA, value);
386 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_WRITE);
395 netsec_write(priv, MAC_REG_CMD, addr | NETSEC_GMAC_CMD_ST_READ);
556 netsec_write(priv, NETSEC_REG_NRM_TX_DONE_TXINT_PKTCNT,
558 netsec_write(priv, NETSEC_REG_NRM_TX_TXINT_TMR,
560 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TXDONE);
561 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_SET, NRM_TX_ST_TMREXP);
568 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_PKTCNT,
570 netsec_write(priv, NETSEC_REG_NRM_RX_RXINT_TMR,
572 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_PKTCNT);
573 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_SET, NRM_RX_ST_TMREXP);
762 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, pkts);
1084 netsec_write(priv, NETSEC_REG_INTEN_SET,
1186 netsec_write(priv, NETSEC_REG_NRM_TX_PKTCNT, 1); /* submit another tx */
1354 netsec_write(priv, reg, readl(ucode + i * 4));
1400 netsec_write(priv, NETSEC_REG_DMA_HM_CTRL,
1402 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL,
1414 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RESET);
1415 netsec_write(priv, NETSEC_REG_SOFT_RST, NETSEC_SOFT_RST_REG_RUN);
1416 netsec_write(priv, NETSEC_REG_COM_INIT, NETSEC_COM_INIT_REG_ALL);
1422 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_UP,
1424 netsec_write(priv, NETSEC_REG_NRM_RX_DESC_START_LW,
1427 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_UP,
1429 netsec_write(priv, NETSEC_REG_NRM_TX_DESC_START_LW,
1433 netsec_write(priv, NETSEC_REG_NRM_TX_CONFIG,
1435 netsec_write(priv, NETSEC_REG_NRM_RX_CONFIG,
1449 netsec_write(priv, NETSEC_REG_DMA_TMR_CTRL, priv->freq / 1000000 - 1);
1450 netsec_write(priv, NETSEC_REG_ADDR_DIS_CORE, 0);
1460 netsec_write(priv, NETSEC_REG_TOP_STATUS,
1468 netsec_write(priv, NETSEC_REG_DMA_MH_CTRL, MH_CTRL__MODE_TRANS);
1469 netsec_write(priv, NETSEC_REG_PKT_CTRL, value);
1476 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, ~0);
1479 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0);
1509 netsec_write(priv, MAC_REG_DESC_SOFT_RST, 1);
1513 netsec_write(priv, MAC_REG_DESC_INIT, 1);
1540 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
1541 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
1563 netsec_write(priv, NETSEC_REG_NRM_RX_INTEN_CLR, ~0);
1564 netsec_write(priv, NETSEC_REG_NRM_TX_INTEN_CLR, ~0);
1590 netsec_write(priv, NETSEC_REG_NRM_TX_STATUS, val);
1594 netsec_write(priv, NETSEC_REG_NRM_RX_STATUS, val);
1598 netsec_write(priv, NETSEC_REG_INTEN_CLR, NETSEC_IRQ_RX | NETSEC_IRQ_TX);
1654 netsec_write(priv, NETSEC_REG_INTEN_SET, NETSEC_IRQ_RX | NETSEC_IRQ_TX);
1676 netsec_write(priv, NETSEC_REG_INTEN_CLR, ~0);
2172 netsec_write(priv, NETSEC_REG_CLK_EN, 0);
2185 netsec_write(priv, NETSEC_REG_CLK_EN, NETSEC_CLK_EN_REG_DOM_D |