Lines Matching refs:pd
86 static inline u32 smsc9420_reg_read(struct smsc9420_pdata *pd, u32 offset)
88 return ioread32(pd->ioaddr + offset);
92 smsc9420_reg_write(struct smsc9420_pdata *pd, u32 offset, u32 value)
94 iowrite32(value, pd->ioaddr + offset);
97 static inline void smsc9420_pci_flush_write(struct smsc9420_pdata *pd)
100 smsc9420_reg_read(pd, ID_REV);
105 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
110 spin_lock_irqsave(&pd->phy_lock, flags);
113 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
114 netif_warn(pd, drv, pd->dev, "MII is busy???\n");
121 smsc9420_reg_write(pd, MII_ACCESS, addr);
125 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
127 reg = (u16)smsc9420_reg_read(pd, MII_DATA);
133 netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
136 spin_unlock_irqrestore(&pd->phy_lock, flags);
143 struct smsc9420_pdata *pd = (struct smsc9420_pdata *)bus->priv;
148 spin_lock_irqsave(&pd->phy_lock, flags);
151 if ((smsc9420_reg_read(pd, MII_ACCESS) & MII_ACCESS_MII_BUSY_)) {
152 netif_warn(pd, drv, pd->dev, "MII is busy???\n");
157 smsc9420_reg_write(pd, MII_DATA, (u32)val);
162 smsc9420_reg_write(pd, MII_ACCESS, addr);
166 if (!(smsc9420_reg_read(pd, MII_ACCESS) &
174 netif_warn(pd, drv, pd->dev, "MII busy timeout!\n");
177 spin_unlock_irqrestore(&pd->phy_lock, flags);
189 static int smsc9420_eeprom_reload(struct smsc9420_pdata *pd)
193 BUG_ON(!pd);
195 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
196 netif_dbg(pd, drv, pd->dev, "%s: Eeprom busy\n", __func__);
200 smsc9420_reg_write(pd, E2P_CMD,
205 if (!(smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_))
209 netif_warn(pd, drv, pd->dev, "%s: Eeprom timed out\n", __func__);
216 struct smsc9420_pdata *pd = netdev_priv(netdev);
219 strlcpy(drvinfo->bus_info, pci_name(pd->pdev),
226 struct smsc9420_pdata *pd = netdev_priv(netdev);
227 return pd->msg_enable;
232 struct smsc9420_pdata *pd = netdev_priv(netdev);
233 pd->msg_enable = data;
246 struct smsc9420_pdata *pd = netdev_priv(dev);
251 regs->version = smsc9420_reg_read(pd, ID_REV);
253 data[j++] = smsc9420_reg_read(pd, i);
264 static void smsc9420_eeprom_enable_access(struct smsc9420_pdata *pd)
266 unsigned int temp = smsc9420_reg_read(pd, GPIO_CFG);
268 smsc9420_reg_write(pd, GPIO_CFG, temp);
272 static int smsc9420_eeprom_send_cmd(struct smsc9420_pdata *pd, u32 op)
277 netif_dbg(pd, hw, pd->dev, "op 0x%08x\n", op);
278 if (smsc9420_reg_read(pd, E2P_CMD) & E2P_CMD_EPC_BUSY_) {
279 netif_warn(pd, hw, pd->dev, "Busy at start\n");
284 smsc9420_reg_write(pd, E2P_CMD, e2cmd);
288 e2cmd = smsc9420_reg_read(pd, E2P_CMD);
292 netif_info(pd, hw, pd->dev, "TIMED OUT\n");
297 netif_info(pd, hw, pd->dev,
305 static int smsc9420_eeprom_read_location(struct smsc9420_pdata *pd,
311 netif_dbg(pd, hw, pd->dev, "address 0x%x\n", address);
312 ret = smsc9420_eeprom_send_cmd(pd, op);
315 data[address] = smsc9420_reg_read(pd, E2P_DATA);
320 static int smsc9420_eeprom_write_location(struct smsc9420_pdata *pd,
326 netif_dbg(pd, hw, pd->dev, "address 0x%x, data 0x%x\n", address, data);
327 ret = smsc9420_eeprom_send_cmd(pd, op);
331 smsc9420_reg_write(pd, E2P_DATA, (u32)data);
332 ret = smsc9420_eeprom_send_cmd(pd, op);
346 struct smsc9420_pdata *pd = netdev_priv(dev);
350 smsc9420_eeprom_enable_access(pd);
354 int ret = smsc9420_eeprom_read_location(pd, i, eeprom_data);
370 struct smsc9420_pdata *pd = netdev_priv(dev);
376 smsc9420_eeprom_enable_access(pd);
377 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWEN_);
378 ret = smsc9420_eeprom_write_location(pd, eeprom->offset, *data);
379 smsc9420_eeprom_send_cmd(pd, E2P_CMD_EPC_CMD_EWDS_);
406 struct smsc9420_pdata *pd = netdev_priv(dev);
412 smsc9420_reg_write(pd, ADDRH, mac_high16);
413 smsc9420_reg_write(pd, ADDRL, mac_low32);
418 struct smsc9420_pdata *pd = netdev_priv(dev);
423 netif_dbg(pd, probe, pd->dev,
428 u32 mac_high16 = smsc9420_reg_read(pd, ADDRH);
429 u32 mac_low32 = smsc9420_reg_read(pd, ADDRL);
439 netif_dbg(pd, probe, pd->dev,
445 netif_dbg(pd, probe, pd->dev,
451 static void smsc9420_stop_tx(struct smsc9420_pdata *pd)
457 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
459 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
463 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_TS_)
469 netif_warn(pd, ifdown, pd->dev, "TX DMAC failed to stop\n");
472 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_TXPS_);
475 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
477 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
478 smsc9420_pci_flush_write(pd);
481 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_TXEN_);
482 smsc9420_reg_write(pd, MAC_CR, mac_cr);
483 smsc9420_pci_flush_write(pd);
486 static void smsc9420_free_tx_ring(struct smsc9420_pdata *pd)
490 BUG_ON(!pd->tx_ring);
492 if (!pd->tx_buffers)
496 struct sk_buff *skb = pd->tx_buffers[i].skb;
499 BUG_ON(!pd->tx_buffers[i].mapping);
500 dma_unmap_single(&pd->pdev->dev,
501 pd->tx_buffers[i].mapping, skb->len,
506 pd->tx_ring[i].status = 0;
507 pd->tx_ring[i].length = 0;
508 pd->tx_ring[i].buffer1 = 0;
509 pd->tx_ring[i].buffer2 = 0;
513 kfree(pd->tx_buffers);
514 pd->tx_buffers = NULL;
516 pd->tx_ring_head = 0;
517 pd->tx_ring_tail = 0;
520 static void smsc9420_free_rx_ring(struct smsc9420_pdata *pd)
524 BUG_ON(!pd->rx_ring);
526 if (!pd->rx_buffers)
530 if (pd->rx_buffers[i].skb)
531 dev_kfree_skb_any(pd->rx_buffers[i].skb);
533 if (pd->rx_buffers[i].mapping)
534 dma_unmap_single(&pd->pdev->dev,
535 pd->rx_buffers[i].mapping,
538 pd->rx_ring[i].status = 0;
539 pd->rx_ring[i].length = 0;
540 pd->rx_ring[i].buffer1 = 0;
541 pd->rx_ring[i].buffer2 = 0;
545 kfree(pd->rx_buffers);
546 pd->rx_buffers = NULL;
548 pd->rx_ring_head = 0;
549 pd->rx_ring_tail = 0;
552 static void smsc9420_stop_rx(struct smsc9420_pdata *pd)
558 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
560 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
561 smsc9420_pci_flush_write(pd);
564 mac_cr = smsc9420_reg_read(pd, MAC_CR) & (~MAC_CR_RXEN_);
565 smsc9420_reg_write(pd, MAC_CR, mac_cr);
566 smsc9420_pci_flush_write(pd);
569 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
571 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
572 smsc9420_pci_flush_write(pd);
576 if (smsc9420_reg_read(pd, DMAC_STATUS) & DMAC_STS_RS_)
582 netif_warn(pd, ifdown, pd->dev,
586 smsc9420_reg_write(pd, DMAC_STATUS, DMAC_STS_RXPS_);
591 struct smsc9420_pdata *pd = dev_id;
596 BUG_ON(!pd);
597 BUG_ON(!pd->ioaddr);
599 int_cfg = smsc9420_reg_read(pd, INT_CFG);
606 int_sts = smsc9420_reg_read(pd, INT_STAT);
609 u32 status = smsc9420_reg_read(pd, DMAC_STATUS);
614 netif_wake_queue(pd->dev);
619 u32 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
621 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
622 smsc9420_pci_flush_write(pd);
625 napi_schedule(&pd->napi);
629 smsc9420_reg_write(pd, DMAC_STATUS, ints_to_clear);
636 spin_lock_irqsave(&pd->int_lock, flags);
637 int_ctl = smsc9420_reg_read(pd, INT_CTL);
639 smsc9420_reg_write(pd, INT_CTL, int_ctl);
640 spin_unlock_irqrestore(&pd->int_lock, flags);
642 smsc9420_reg_write(pd, INT_STAT, INT_STAT_SW_INT_);
643 pd->software_irq_signal = true;
650 smsc9420_pci_flush_write(pd);
658 struct smsc9420_pdata *pd = netdev_priv(dev);
659 const int irq = pd->pdev->irq;
667 static void smsc9420_dmac_soft_reset(struct smsc9420_pdata *pd)
669 smsc9420_reg_write(pd, BUS_MODE, BUS_MODE_SWR_);
670 smsc9420_reg_read(pd, BUS_MODE);
672 if (smsc9420_reg_read(pd, BUS_MODE) & BUS_MODE_SWR_)
673 netif_warn(pd, drv, pd->dev, "Software reset not cleared\n");
678 struct smsc9420_pdata *pd = netdev_priv(dev);
682 BUG_ON(!pd);
686 spin_lock_irqsave(&pd->int_lock, flags);
687 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
688 smsc9420_reg_write(pd, INT_CFG, int_cfg);
689 spin_unlock_irqrestore(&pd->int_lock, flags);
692 napi_disable(&pd->napi);
694 smsc9420_stop_tx(pd);
695 smsc9420_free_tx_ring(pd);
697 smsc9420_stop_rx(pd);
698 smsc9420_free_rx_ring(pd);
700 free_irq(pd->pdev->irq, pd);
702 smsc9420_dmac_soft_reset(pd);
707 mdiobus_unregister(pd->mii_bus);
708 mdiobus_free(pd->mii_bus);
737 static void smsc9420_rx_handoff(struct smsc9420_pdata *pd, const int index,
740 struct net_device *dev = pd->dev;
748 if (pd->rx_csum)
754 dma_unmap_single(&pd->pdev->dev, pd->rx_buffers[index].mapping,
756 pd->rx_buffers[index].mapping = 0;
758 skb = pd->rx_buffers[index].skb;
759 pd->rx_buffers[index].skb = NULL;
761 if (pd->rx_csum) {
776 static int smsc9420_alloc_rx_buffer(struct smsc9420_pdata *pd, int index)
778 struct sk_buff *skb = netdev_alloc_skb(pd->dev, PKT_BUF_SZ);
781 BUG_ON(pd->rx_buffers[index].skb);
782 BUG_ON(pd->rx_buffers[index].mapping);
787 mapping = dma_map_single(&pd->pdev->dev, skb_tail_pointer(skb),
789 if (dma_mapping_error(&pd->pdev->dev, mapping)) {
791 netif_warn(pd, rx_err, pd->dev, "pci_map_single failed!\n");
795 pd->rx_buffers[index].skb = skb;
796 pd->rx_buffers[index].mapping = mapping;
797 pd->rx_ring[index].buffer1 = mapping + NET_IP_ALIGN;
798 pd->rx_ring[index].status = RDES0_OWN_;
804 static void smsc9420_alloc_new_rx_buffers(struct smsc9420_pdata *pd)
806 while (pd->rx_ring_tail != pd->rx_ring_head) {
807 if (smsc9420_alloc_rx_buffer(pd, pd->rx_ring_tail))
810 pd->rx_ring_tail = (pd->rx_ring_tail + 1) % RX_RING_SIZE;
816 struct smsc9420_pdata *pd =
818 struct net_device *dev = pd->dev;
824 status = pd->rx_ring[pd->rx_ring_head].status;
831 smsc9420_rx_handoff(pd, pd->rx_ring_head, status);
832 pd->rx_ring_head = (pd->rx_ring_head + 1) % RX_RING_SIZE;
833 smsc9420_alloc_new_rx_buffers(pd);
836 drop_frame_cnt = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
841 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
842 smsc9420_pci_flush_write(pd);
845 napi_complete_done(&pd->napi, work_done);
848 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
850 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
851 smsc9420_pci_flush_write(pd);
887 struct smsc9420_pdata *pd = netdev_priv(dev);
889 while (pd->tx_ring_tail != pd->tx_ring_head) {
890 int index = pd->tx_ring_tail;
894 status = pd->tx_ring[index].status;
895 length = pd->tx_ring[index].length;
903 BUG_ON(!pd->tx_buffers[index].skb);
904 BUG_ON(!pd->tx_buffers[index].mapping);
906 dma_unmap_single(&pd->pdev->dev,
907 pd->tx_buffers[index].mapping,
908 pd->tx_buffers[index].skb->len,
910 pd->tx_buffers[index].mapping = 0;
912 dev_kfree_skb_any(pd->tx_buffers[index].skb);
913 pd->tx_buffers[index].skb = NULL;
915 pd->tx_ring[index].buffer1 = 0;
918 pd->tx_ring_tail = (pd->tx_ring_tail + 1) % TX_RING_SIZE;
925 struct smsc9420_pdata *pd = netdev_priv(dev);
927 int index = pd->tx_ring_head;
930 (((pd->tx_ring_head + 2) % TX_RING_SIZE) == pd->tx_ring_tail);
935 BUG_ON(pd->tx_ring[index].status & TDES0_OWN_);
936 BUG_ON(pd->tx_buffers[index].skb);
937 BUG_ON(pd->tx_buffers[index].mapping);
939 mapping = dma_map_single(&pd->pdev->dev, skb->data, skb->len,
941 if (dma_mapping_error(&pd->pdev->dev, mapping)) {
942 netif_warn(pd, tx_err, pd->dev,
947 pd->tx_buffers[index].skb = skb;
948 pd->tx_buffers[index].mapping = mapping;
953 netif_stop_queue(pd->dev);
960 pd->tx_ring[index].buffer1 = mapping;
961 pd->tx_ring[index].length = tmp_desc1;
965 pd->tx_ring_head = (pd->tx_ring_head + 1) % TX_RING_SIZE;
968 pd->tx_ring[index].status = TDES0_OWN_;
974 smsc9420_reg_write(pd, TX_POLL_DEMAND, 1);
975 smsc9420_pci_flush_write(pd);
982 struct smsc9420_pdata *pd = netdev_priv(dev);
983 u32 counter = smsc9420_reg_read(pd, MISS_FRAME_CNTR);
991 struct smsc9420_pdata *pd = netdev_priv(dev);
992 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
995 netif_dbg(pd, hw, pd->dev, "Promiscuous Mode Enabled\n");
1000 netif_dbg(pd, hw, pd->dev, "Receive all Multicast Enabled\n");
1008 netif_dbg(pd, hw, pd->dev, "Multicast filter enabled\n");
1019 smsc9420_reg_write(pd, HASHH, hash_hi);
1020 smsc9420_reg_write(pd, HASHL, hash_lo);
1026 netif_dbg(pd, hw, pd->dev, "Receive own packets only\n");
1027 smsc9420_reg_write(pd, HASHH, 0);
1028 smsc9420_reg_write(pd, HASHL, 0);
1035 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1036 smsc9420_pci_flush_write(pd);
1039 static void smsc9420_phy_update_flowcontrol(struct smsc9420_pdata *pd)
1041 struct net_device *dev = pd->dev;
1055 netif_info(pd, link, pd->dev, "rx pause %s, tx pause %s\n",
1059 netif_info(pd, link, pd->dev, "half duplex\n");
1063 smsc9420_reg_write(pd, FLOW, flow);
1070 struct smsc9420_pdata *pd = netdev_priv(dev);
1074 if (phy_dev->duplex != pd->last_duplex) {
1075 u32 mac_cr = smsc9420_reg_read(pd, MAC_CR);
1077 netif_dbg(pd, link, pd->dev, "full duplex mode\n");
1080 netif_dbg(pd, link, pd->dev, "half duplex mode\n");
1083 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1085 smsc9420_phy_update_flowcontrol(pd);
1086 pd->last_duplex = phy_dev->duplex;
1090 if (carrier != pd->last_carrier) {
1092 netif_dbg(pd, link, pd->dev, "carrier OK\n");
1094 netif_dbg(pd, link, pd->dev, "no carrier\n");
1095 pd->last_carrier = carrier;
1101 struct smsc9420_pdata *pd = netdev_priv(dev);
1107 phydev = mdiobus_get_phy(pd->mii_bus, 1);
1128 pd->last_duplex = -1;
1129 pd->last_carrier = -1;
1136 struct smsc9420_pdata *pd = netdev_priv(dev);
1139 pd->mii_bus = mdiobus_alloc();
1140 if (!pd->mii_bus) {
1144 pd->mii_bus->name = DRV_MDIONAME;
1145 snprintf(pd->mii_bus->id, MII_BUS_ID_SIZE, "%x",
1146 (pd->pdev->bus->number << 8) | pd->pdev->devfn);
1147 pd->mii_bus->priv = pd;
1148 pd->mii_bus->read = smsc9420_mii_read;
1149 pd->mii_bus->write = smsc9420_mii_write;
1152 pd->mii_bus->phy_mask = ~(1 << 1);
1154 if (mdiobus_register(pd->mii_bus)) {
1155 netif_warn(pd, probe, pd->dev, "Error registering mii bus\n");
1160 netif_warn(pd, probe, pd->dev, "Error probing mii bus\n");
1167 mdiobus_unregister(pd->mii_bus);
1169 mdiobus_free(pd->mii_bus);
1174 static int smsc9420_alloc_tx_ring(struct smsc9420_pdata *pd)
1178 BUG_ON(!pd->tx_ring);
1180 pd->tx_buffers = kmalloc_array(TX_RING_SIZE,
1183 if (!pd->tx_buffers)
1188 pd->tx_buffers[i].skb = NULL;
1189 pd->tx_buffers[i].mapping = 0;
1190 pd->tx_ring[i].status = 0;
1191 pd->tx_ring[i].length = 0;
1192 pd->tx_ring[i].buffer1 = 0;
1193 pd->tx_ring[i].buffer2 = 0;
1195 pd->tx_ring[TX_RING_SIZE - 1].length = TDES1_TER_;
1198 pd->tx_ring_head = 0;
1199 pd->tx_ring_tail = 0;
1201 smsc9420_reg_write(pd, TX_BASE_ADDR, pd->tx_dma_addr);
1202 smsc9420_pci_flush_write(pd);
1207 static int smsc9420_alloc_rx_ring(struct smsc9420_pdata *pd)
1211 BUG_ON(!pd->rx_ring);
1213 pd->rx_buffers = kmalloc_array(RX_RING_SIZE,
1216 if (pd->rx_buffers == NULL)
1221 pd->rx_ring[i].status = 0;
1222 pd->rx_ring[i].length = PKT_BUF_SZ;
1223 pd->rx_ring[i].buffer2 = 0;
1224 pd->rx_buffers[i].skb = NULL;
1225 pd->rx_buffers[i].mapping = 0;
1227 pd->rx_ring[RX_RING_SIZE - 1].length = (PKT_BUF_SZ | RDES1_RER_);
1231 if (smsc9420_alloc_rx_buffer(pd, i)) {
1232 netif_warn(pd, ifup, pd->dev,
1238 pd->rx_ring_head = 0;
1239 pd->rx_ring_tail = 0;
1241 smsc9420_reg_write(pd, VLAN1, ETH_P_8021Q);
1242 netif_dbg(pd, ifup, pd->dev, "VLAN1 = 0x%08x\n",
1243 smsc9420_reg_read(pd, VLAN1));
1245 if (pd->rx_csum) {
1247 u32 coe = smsc9420_reg_read(pd, COE_CR) | RX_COE_EN;
1248 smsc9420_reg_write(pd, COE_CR, coe);
1249 netif_dbg(pd, ifup, pd->dev, "COE_CR = 0x%08x\n", coe);
1252 smsc9420_reg_write(pd, RX_BASE_ADDR, pd->rx_dma_addr);
1253 smsc9420_pci_flush_write(pd);
1258 smsc9420_free_rx_ring(pd);
1265 struct smsc9420_pdata *pd = netdev_priv(dev);
1267 const int irq = pd->pdev->irq;
1272 netif_warn(pd, ifup, pd->dev,
1281 spin_lock_irqsave(&pd->int_lock, flags);
1282 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1283 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1284 smsc9420_reg_write(pd, INT_CTL, 0);
1285 spin_unlock_irqrestore(&pd->int_lock, flags);
1286 smsc9420_reg_write(pd, DMAC_INTR_ENA, 0);
1287 smsc9420_reg_write(pd, INT_STAT, 0xFFFFFFFF);
1288 smsc9420_pci_flush_write(pd);
1290 result = request_irq(irq, smsc9420_isr, IRQF_SHARED, DRV_NAME, pd);
1292 netif_warn(pd, ifup, pd->dev, "Unable to use IRQ = %d\n", irq);
1297 smsc9420_dmac_soft_reset(pd);
1300 smsc9420_reg_write(pd, MAC_CR, 0);
1305 smsc9420_reg_write(pd, GPIO_CFG,
1314 smsc9420_reg_write(pd, BUS_MODE, bus_mode);
1316 smsc9420_pci_flush_write(pd);
1319 smsc9420_reg_write(pd, BUS_CFG, BUS_CFG_RXTXWEIGHT_4_1);
1321 smsc9420_reg_write(pd, DMAC_CONTROL,
1324 smsc9420_pci_flush_write(pd);
1327 netif_dbg(pd, ifup, pd->dev, "Testing ISR using IRQ %d\n", irq);
1328 pd->software_irq_signal = false;
1330 spin_lock_irqsave(&pd->int_lock, flags);
1332 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1335 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1338 int_ctl = smsc9420_reg_read(pd, INT_CTL) | INT_CTL_SW_INT_EN_;
1339 smsc9420_reg_write(pd, INT_CTL, int_ctl);
1340 spin_unlock_irqrestore(&pd->int_lock, flags);
1341 smsc9420_pci_flush_write(pd);
1345 if (pd->software_irq_signal)
1351 spin_lock_irqsave(&pd->int_lock, flags);
1352 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1353 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1354 spin_unlock_irqrestore(&pd->int_lock, flags);
1356 if (!pd->software_irq_signal) {
1357 netif_warn(pd, ifup, pd->dev, "ISR failed signaling test\n");
1362 netif_dbg(pd, ifup, pd->dev, "ISR passed test using IRQ %d\n", irq);
1364 result = smsc9420_alloc_tx_ring(pd);
1366 netif_warn(pd, ifup, pd->dev,
1372 result = smsc9420_alloc_rx_ring(pd);
1374 netif_warn(pd, ifup, pd->dev,
1382 netif_warn(pd, ifup, pd->dev, "Failed to initialize Phy\n");
1390 napi_enable(&pd->napi);
1393 mac_cr = smsc9420_reg_read(pd, MAC_CR) | MAC_CR_TXEN_ | MAC_CR_RXEN_;
1394 smsc9420_reg_write(pd, MAC_CR, mac_cr);
1396 dmac_control = smsc9420_reg_read(pd, DMAC_CONTROL);
1398 smsc9420_reg_write(pd, DMAC_CONTROL, dmac_control);
1399 smsc9420_pci_flush_write(pd);
1401 dma_intr_ena = smsc9420_reg_read(pd, DMAC_INTR_ENA);
1404 smsc9420_reg_write(pd, DMAC_INTR_ENA, dma_intr_ena);
1405 smsc9420_pci_flush_write(pd);
1409 smsc9420_reg_write(pd, RX_POLL_DEMAND, 1);
1412 spin_lock_irqsave(&pd->int_lock, flags);
1413 int_cfg = smsc9420_reg_read(pd, INT_CFG) | INT_CFG_IRQ_EN_;
1414 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1415 spin_unlock_irqrestore(&pd->int_lock, flags);
1420 smsc9420_free_rx_ring(pd);
1422 smsc9420_free_tx_ring(pd);
1424 free_irq(irq, pd);
1432 struct smsc9420_pdata *pd = netdev_priv(dev);
1437 spin_lock_irqsave(&pd->int_lock, flags);
1438 int_cfg = smsc9420_reg_read(pd, INT_CFG) & (~INT_CFG_IRQ_EN_);
1439 smsc9420_reg_write(pd, INT_CFG, int_cfg);
1440 spin_unlock_irqrestore(&pd->int_lock, flags);
1444 smsc9420_stop_tx(pd);
1445 smsc9420_free_tx_ring(pd);
1447 napi_disable(&pd->napi);
1448 smsc9420_stop_rx(pd);
1449 smsc9420_free_rx_ring(pd);
1451 free_irq(pd->pdev->irq, pd);
1497 struct smsc9420_pdata *pd;
1513 dev = alloc_etherdev(sizeof(*pd));
1544 pd = netdev_priv(dev);
1547 pd->rx_ring = dma_alloc_coherent(&pdev->dev,
1549 &pd->rx_dma_addr, GFP_KERNEL);
1551 if (!pd->rx_ring)
1555 pd->tx_ring = (pd->rx_ring + RX_RING_SIZE);
1556 pd->tx_dma_addr = pd->rx_dma_addr +
1559 pd->pdev = pdev;
1560 pd->dev = dev;
1561 pd->ioaddr = virt_addr;
1562 pd->msg_enable = smsc_debug;
1563 pd->rx_csum = true;
1565 netif_dbg(pd, probe, pd->dev, "lan_base=0x%08lx\n", (ulong)virt_addr);
1567 id_rev = smsc9420_reg_read(pd, ID_REV);
1570 netif_info(pd, probe, pd->dev,
1574 netif_warn(pd, probe, pd->dev, "LAN9420 NOT identified\n");
1575 netif_warn(pd, probe, pd->dev, "ID_REV=0x%08X\n", id_rev);
1579 smsc9420_dmac_soft_reset(pd);
1580 smsc9420_eeprom_reload(pd);
1586 netif_napi_add(dev, &pd->napi, smsc9420_rx_poll, NAPI_WEIGHT);
1590 netif_warn(pd, probe, pd->dev, "error %i registering device\n",
1597 spin_lock_init(&pd->int_lock);
1598 spin_lock_init(&pd->phy_lock);
1607 pd->rx_ring, pd->rx_dma_addr);
1623 struct smsc9420_pdata *pd;
1629 pd = netdev_priv(dev);
1633 BUG_ON(pd->tx_buffers);
1634 BUG_ON(pd->rx_buffers);
1636 BUG_ON(!pd->tx_ring);
1637 BUG_ON(!pd->rx_ring);
1641 pd->rx_ring, pd->rx_dma_addr);
1643 iounmap(pd->ioaddr - LAN9420_CPSR_ENDIAN_OFFSET);