Lines Matching refs:lp
65 #define SMC_IO_SHIFT (lp->io_shift)
71 SMC_16BIT(lp) ? readw((a) + __smc_r) : \
72 SMC_8BIT(lp) ? SMC_inw_b(a, __smc_r) : \
78 #define SMC_outw(lp, v, a, r) \
81 if (SMC_16BIT(lp)) \
82 __SMC_outw(lp, __v, a, __smc_r); \
83 else if (SMC_8BIT(lp)) \
111 #define __SMC_outw(lp, v, a, r) \
114 (lp)->cfg.pxa_u16_align4)
127 #define SMC_outw(lp, v, a, r) outw(v, (a) + (r) - 0xa0000000)
147 #define SMC_outw(lp, v, a, r) writew(v, (a) + (r))
179 #define SMC_outw(lp, v, a, r) writew(_swapw(v), (a) + (r))
207 #define SMC_IO_SHIFT (lp->io_shift)
213 #define SMC_outw(lp, v, a, r) iowrite16(v, (a) + (r))
297 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
299 smc_pxa_dma_inpump(struct smc_local *lp, u_char *buf, int len)
307 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
308 tx = dmaengine_prep_slave_single(lp->dma_chan, dmabuf, len,
312 dma_async_issue_pending(lp->dma_chan);
314 status = dmaengine_tx_status(lp->dma_chan, cookie,
319 dmaengine_terminate_all(lp->dma_chan);
321 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
325 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
332 if (!lp->dma_chan) {
347 config.src_addr = lp->physaddr + reg;
348 config.dst_addr = lp->physaddr + reg;
351 ret = dmaengine_slave_config(lp->dma_chan, &config);
353 dev_err(lp->device, "dma channel configuration failed: %d\n",
359 smc_pxa_dma_inpump(lp, buf, len);
366 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
368 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
375 if (!lp->dma_chan) {
390 config.src_addr = lp->physaddr + reg;
391 config.dst_addr = lp->physaddr + reg;
394 ret = dmaengine_slave_config(lp->dma_chan, &config);
396 dev_err(lp->device, "dma channel configuration failed: %d\n",
402 smc_pxa_dma_inpump(lp, buf, len);
430 #define SMC_outw(lp, x, ioaddr, reg) SMC_outw_b(x, ioaddr, reg)
489 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
508 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
527 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
544 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
549 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
554 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
580 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
592 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
597 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
598 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
599 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
604 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
609 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
622 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
636 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
641 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
647 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
652 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
655 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
659 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
667 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
672 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
677 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
690 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
691 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
692 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
693 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
698 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
709 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
715 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
722 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
846 #define SMC_REG(lp, reg, bank) \
848 int __b = SMC_CURRENT_BANK(lp); \
857 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
869 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
871 #define SMC_GET_PN(lp) \
872 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
873 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
875 #define SMC_SET_PN(lp, x) \
877 if (SMC_MUST_ALIGN_WRITE(lp)) \
878 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
879 else if (SMC_8BIT(lp)) \
880 SMC_outb(x, ioaddr, PN_REG(lp)); \
882 SMC_outw(lp, x, ioaddr, PN_REG(lp)); \
885 #define SMC_GET_AR(lp) \
886 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
887 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
889 #define SMC_GET_TXFIFO(lp) \
890 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
891 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
893 #define SMC_GET_RXFIFO(lp) \
894 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
895 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
897 #define SMC_GET_INT(lp) \
898 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
899 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
901 #define SMC_ACK_INT(lp, x) \
903 if (SMC_8BIT(lp)) \
904 SMC_outb(x, ioaddr, INT_REG(lp)); \
909 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
910 SMC_outw(lp, __mask | (x), ioaddr, INT_REG(lp)); \
915 #define SMC_GET_INT_MASK(lp) \
916 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
917 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
919 #define SMC_SET_INT_MASK(lp, x) \
921 if (SMC_8BIT(lp)) \
922 SMC_outb(x, ioaddr, IM_REG(lp)); \
924 SMC_outw(lp, (x) << 8, ioaddr, INT_REG(lp)); \
927 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
929 #define SMC_SELECT_BANK(lp, x) \
931 if (SMC_MUST_ALIGN_WRITE(lp)) \
934 SMC_outw(lp, x, ioaddr, BANK_SELECT); \
937 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
939 #define SMC_SET_BASE(lp, x) SMC_outw(lp, x, ioaddr, BASE_REG(lp))
941 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
943 #define SMC_SET_CONFIG(lp, x) SMC_outw(lp, x, ioaddr, CONFIG_REG(lp))
945 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
947 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
949 #define SMC_SET_CTL(lp, x) SMC_outw(lp, x, ioaddr, CTL_REG(lp))
951 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
953 #define SMC_GET_GP(lp) SMC_inw(ioaddr, GP_REG(lp))
955 #define SMC_SET_GP(lp, x) \
957 if (SMC_MUST_ALIGN_WRITE(lp)) \
958 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 1)); \
960 SMC_outw(lp, x, ioaddr, GP_REG(lp)); \
963 #define SMC_SET_MII(lp, x) SMC_outw(lp, x, ioaddr, MII_REG(lp))
965 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
967 #define SMC_SET_MIR(lp, x) SMC_outw(lp, x, ioaddr, MIR_REG(lp))
969 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
971 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(lp, x, ioaddr, MMU_CMD_REG(lp))
973 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
975 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
977 #define SMC_SET_PTR(lp, x) \
979 if (SMC_MUST_ALIGN_WRITE(lp)) \
980 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
982 SMC_outw(lp, x, ioaddr, PTR_REG(lp)); \
985 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
987 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
989 #define SMC_SET_RCR(lp, x) SMC_outw(lp, x, ioaddr, RCR_REG(lp))
991 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
993 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
995 #define SMC_SET_RPC(lp, x) \
997 if (SMC_MUST_ALIGN_WRITE(lp)) \
998 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1000 SMC_outw(lp, x, ioaddr, RPC_REG(lp)); \
1003 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
1005 #define SMC_SET_TCR(lp, x) SMC_outw(lp, x, ioaddr, TCR_REG(lp))
1008 #define SMC_GET_MAC_ADDR(lp, addr) \
1011 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1013 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1015 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1020 #define SMC_SET_MAC_ADDR(lp, addr) \
1022 SMC_outw(lp, addr[0] | (addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1023 SMC_outw(lp, addr[2] | (addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1024 SMC_outw(lp, addr[4] | (addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1027 #define SMC_SET_MCAST(lp, x) \
1030 SMC_outw(lp, mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1031 SMC_outw(lp, mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1032 SMC_outw(lp, mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1033 SMC_outw(lp, mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1036 #define SMC_PUT_PKT_HDR(lp, status, length) \
1038 if (SMC_32BIT(lp)) \
1040 DATA_REG(lp)); \
1042 SMC_outw(lp, status, ioaddr, DATA_REG(lp)); \
1043 SMC_outw(lp, length, ioaddr, DATA_REG(lp)); \
1047 #define SMC_GET_PKT_HDR(lp, status, length) \
1049 if (SMC_32BIT(lp)) { \
1050 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1054 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1055 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1059 #define SMC_PUSH_DATA(lp, p, l) \
1061 if (SMC_32BIT(lp)) { \
1067 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1070 if (SMC_CAN_USE_DATACS && lp->datacs) \
1071 __ioaddr = lp->datacs; \
1072 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1075 SMC_outsw(ioaddr, DATA_REG(lp), __ptr, 1); \
1077 } else if (SMC_16BIT(lp)) \
1078 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1079 else if (SMC_8BIT(lp)) \
1080 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1083 #define SMC_PULL_DATA(lp, p, l) \
1085 if (SMC_32BIT(lp)) { \
1105 SMC_SET_PTR(lp, \
1108 if (SMC_CAN_USE_DATACS && lp->datacs) \
1109 __ioaddr = lp->datacs; \
1111 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1112 } else if (SMC_16BIT(lp)) \
1113 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1114 else if (SMC_8BIT(lp)) \
1115 SMC_insb(ioaddr, DATA_REG(lp), p, l); \