Lines Matching refs:outw
146 #define SMC_SELECT_BANK(x) { outw(x, ioaddr + BANK_SELECT); }
262 #define set_bits(v, p) outw(inw(p)|(v), (p))
263 #define mask_bits(v, p) outw(inw(p)&(v), (p))
548 outw(MOT_EEPROM + i, ioaddr + POINTER);
550 outw((CTL_RELOAD | CTL_EE_SELECT), ioaddr + CONTROL);
772 outw(0, ioaddr + CONTROL);
1043 outw(save, ioaddr + BANK_SELECT);
1095 outw(0, ioaddr + INTERRUPT);
1102 outw(CTL_POWERDOWN, ioaddr + CONTROL );
1144 outw(packet_no, ioaddr + PNR_ARR);
1146 outw(PTR_AUTOINC , ioaddr + POINTER);
1157 outw(0, ioaddr + DATA_1);
1158 outw(length + 6, ioaddr + DATA_1);
1162 outw((length & 1) ? 0x2000 | buf[length-1] : 0, ioaddr + DATA_1);
1166 outw(((IM_TX_INT|IM_TX_EMPTY_INT)<<8) |
1171 outw(MC_ENQUEUE , ioaddr + MMU_CMD);
1234 outw(MC_RESET, ioaddr + MMU_CMD);
1239 outw(MC_ALLOC | num_pages, ioaddr + MMU_CMD);
1244 outw((ir&0xff00) | IM_ALLOC_INT, ioaddr + INTERRUPT);
1253 outw((IM_ALLOC_INT << 8) | (ir & 0xff00), ioaddr + INTERRUPT);
1274 outw(packet_no, ioaddr + PNR_ARR);
1277 outw(PTR_AUTOINC | PTR_READ | 0, ioaddr + POINTER);
1294 outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR);
1297 outw(MC_FREEPKT, ioaddr + MMU_CMD); /* Free the packet memory. */
1302 outw(saved_packet, ioaddr + PNR_ARR);
1329 outw(inw(ioaddr + TCR) | TCR_ENABLE | smc->duplex, ioaddr + TCR);
1333 outw(CTL_AUTO_RELEASE | 0x0000, ioaddr + CONTROL);
1334 outw(CTL_AUTO_RELEASE | CTL_TE_ENABLE | CTL_CR_ENABLE,
1374 outw(0, ioaddr + INTERRUPT);
1391 outw(IM_TX_INT, ioaddr + INTERRUPT);
1395 outw(IM_TX_EMPTY_INT, ioaddr + INTERRUPT);
1417 outw(IM_RX_OVRN_INT, ioaddr + INTERRUPT);
1427 outw((mask<<8), ioaddr + INTERRUPT);
1428 outw(saved_pointer, ioaddr + POINTER);
1485 outw(PTR_READ | PTR_RCV | PTR_AUTOINC, ioaddr + POINTER);
1503 outw(MC_RELEASE, ioaddr + MMU_CMD);
1529 outw(MC_RELEASE, ioaddr + MMU_CMD);
1576 outw(rx_cfg_setting, ioaddr + RCR);
1621 outw(smc->cfg | CFG_AUI_SELECT, ioaddr + CONFIG);
1627 outw(smc->cfg, ioaddr + CONFIG);
1648 outw(RCR_SOFTRESET, ioaddr + RCR);
1652 outw(RCR_CLEAR, ioaddr + RCR);
1653 outw(TCR_CLEAR, ioaddr + TCR);
1660 outw(CTL_AUTO_RELEASE | CTL_TE_ENABLE | CTL_CR_ENABLE,
1665 outw((dev->if_port == 2 ? OSI_AUI_PWR : 0) |
1671 outw((dev->dev_addr[i+1]<<8)+dev->dev_addr[i],
1676 outw(MC_RESET, ioaddr + MMU_CMD);
1677 outw(0, ioaddr + INTERRUPT);
1681 outw(((smc->cfg & CFG_MII_SELECT) ? 0 : TCR_MONCSN) |
1701 outw((IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT) << 8,
1731 outw(MC_RESET, ioaddr + MMU_CMD);
1788 outw(inw(ioaddr + TCR) | smc->duplex, ioaddr + TCR);
1895 outw(tmp, ioaddr + TCR);