Lines Matching defs:sr32
211 #define sr32(reg) ioread32(ioaddr + (reg))
337 rfcrSave = sr32(rfcr);
382 if (sr32(mear) & EEGNT) {
543 sw32(cr, ACCESSMODE | sr32(cr));
570 ret = (sr32(CFGPMC) & PMESP) >> 27;
805 #define eeprom_delay() sr32(mear)
845 retval = (retval << 1) | ((sr32(mear) & EEDO) ? 1 : 0);
859 #define mdio_delay() sr32(mear)
919 retval = (retval << 1) | ((sr32(mear) & MDIO) ? 1 : 0);
1064 sw32(cr, RxENA | sr32(cr));
1094 rfcrSave = sr32(rfcr);
1108 net_dev->name, i, sr32(rfdr));
1146 net_dev->name, sr32(txdp));
1207 net_dev->name, sr32(rxdp));
1378 sw32(cfg, ~EXD & sr32(cfg));
1382 sw32(cfg, EXD | sr32(cfg));
1408 if (sr32( cfg) & EDB_MASTER_EN) {
1551 net_dev->name, sr32(cr), sr32(isr));
1629 sw32(cr, TxENA | sr32(cr));
1682 status = sr32(isr);
1717 net_dev->name, sr32(isr));
1879 sw32(cr , RxENA | sr32(cr));
1977 sw32(cr, RxDIS | TxDIS | sr32(cr));
2127 pmctrl_bits = sr32(pmctrl);
2155 if (sr32(mear) & EEGNT) {
2430 cr_saved = sr32(cr);
2433 sw32(txcfg, sr32(txcfg) | TxMLB);
2434 sw32(rxcfg, sr32(rxcfg) | RxATX);
2460 sw32(cr, RxRESET | TxRESET | RESET | sr32(cr));
2464 status ^= sr32(isr) & status;
2515 sw32(cr, RxDIS | TxDIS | sr32(cr));
2544 sw32(cr, RxENA | sr32(cr));