Lines Matching defs:sis_priv
259 struct sis900_private *sis_priv = netdev_priv(net_dev);
260 void __iomem *ioaddr = sis_priv->ioaddr;
332 struct sis900_private *sis_priv = netdev_priv(net_dev);
333 void __iomem *ioaddr = sis_priv->ioaddr;
376 struct sis900_private *sis_priv = netdev_priv(net_dev);
377 void __iomem *ioaddr = sis_priv->ioaddr;
428 struct sis900_private *sis_priv;
475 sis_priv = netdev_priv(net_dev);
476 sis_priv->ioaddr = ioaddr;
477 sis_priv->pci_dev = pci_dev;
478 spin_lock_init(&sis_priv->lock);
480 sis_priv->eeprom_size = 24;
490 sis_priv->tx_ring = ring_space;
491 sis_priv->tx_ring_dma = ring_dma;
499 sis_priv->rx_ring = ring_space;
500 sis_priv->rx_ring_dma = ring_dma;
508 sis_priv->msg_enable = sis900_debug;
510 sis_priv->msg_enable = SIS900_DEF_MSG;
512 sis_priv->mii_info.dev = net_dev;
513 sis_priv->mii_info.mdio_read = mdio_read;
514 sis_priv->mii_info.mdio_write = mdio_write;
515 sis_priv->mii_info.phy_id_mask = 0x1f;
516 sis_priv->mii_info.reg_num_mask = 0x1f;
519 sis_priv->chipset_rev = pci_dev->revision;
520 if(netif_msg_probe(sis_priv))
523 dev_name, sis_priv->chipset_rev);
526 if (sis_priv->chipset_rev == SIS630E_900_REV)
528 else if ((sis_priv->chipset_rev > 0x81) && (sis_priv->chipset_rev <= 0x90) )
530 else if (sis_priv->chipset_rev == SIS96x_900_REV)
542 if (sis_priv->chipset_rev == SIS630ET_900_REV)
556 sis_priv->host_bridge_rev = dev->revision;
571 if (netif_msg_probe(sis_priv) && (ret & PME_D3C) == 0)
577 dma_free_coherent(&pci_dev->dev, RX_TOTAL_SIZE, sis_priv->rx_ring,
578 sis_priv->rx_ring_dma);
580 dma_free_coherent(&pci_dev->dev, TX_TOTAL_SIZE, sis_priv->tx_ring,
581 sis_priv->tx_ring_dma);
600 struct sis900_private *sis_priv = netdev_priv(net_dev);
601 const char *dev_name = pci_name(sis_priv->pci_dev);
606 sis_priv->mii = NULL;
619 if (netif_msg_probe(sis_priv))
627 mii_phy = sis_priv->first_mii;
641 mii_phy->next = sis_priv->mii;
642 sis_priv->mii = mii_phy;
643 sis_priv->first_mii = mii_phy;
667 if (sis_priv->mii == NULL) {
673 sis_priv->mii = NULL;
677 if ((sis_priv->mii->phy_id0 == 0x001D) &&
678 ((sis_priv->mii->phy_id1&0xFFF0) == 0x8000))
679 status = sis900_reset_phy(net_dev, sis_priv->cur_phy);
682 if ((sis_priv->mii->phy_id0 == 0x0015) &&
683 ((sis_priv->mii->phy_id1&0xFFF0) == 0xF440))
684 mdio_write(net_dev, sis_priv->cur_phy, 0x0018, 0xD200);
690 poll_bit ^= (mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS) & poll_bit);
699 if (sis_priv->chipset_rev == SIS630E_900_REV) {
701 mdio_write(net_dev, sis_priv->cur_phy, MII_ANADV, 0x05e1);
702 mdio_write(net_dev, sis_priv->cur_phy, MII_CONFIG1, 0x22);
703 mdio_write(net_dev, sis_priv->cur_phy, MII_CONFIG2, 0xff00);
704 mdio_write(net_dev, sis_priv->cur_phy, MII_MASK, 0xffc0);
705 //mdio_write(net_dev, sis_priv->cur_phy, MII_CONTROL, 0x1000);
708 if (sis_priv->mii->status & MII_STAT_LINK)
727 struct sis900_private *sis_priv = netdev_priv(net_dev);
732 for (phy=sis_priv->first_mii; phy; phy=phy->next) {
756 default_phy = sis_priv->first_mii;
758 if (sis_priv->mii != default_phy) {
759 sis_priv->mii = default_phy;
760 sis_priv->cur_phy = default_phy->phy_addr;
762 pci_name(sis_priv->pci_dev), sis_priv->cur_phy);
765 sis_priv->mii_info.phy_id = sis_priv->cur_phy;
767 status = mdio_read(net_dev, sis_priv->cur_phy, MII_CONTROL);
770 mdio_write(net_dev, sis_priv->cur_phy, MII_CONTROL, status);
771 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
772 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1035 struct sis900_private *sis_priv = netdev_priv(net_dev);
1036 void __iomem *ioaddr = sis_priv->ioaddr;
1043 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1045 ret = request_irq(sis_priv->pci_dev->irq, sis900_interrupt, IRQF_SHARED,
1060 sis900_set_mode(sis_priv, HW_SPEED_10_MBPS, FDX_CAPABLE_HALF_SELECTED);
1067 sis900_check_mode(net_dev, sis_priv->mii);
1071 timer_setup(&sis_priv->timer, sis900_timer, 0);
1072 sis_priv->timer.expires = jiffies + HZ;
1073 add_timer(&sis_priv->timer);
1089 struct sis900_private *sis_priv = netdev_priv(net_dev);
1090 void __iomem *ioaddr = sis_priv->ioaddr;
1106 if (netif_msg_hw(sis_priv)) {
1126 struct sis900_private *sis_priv = netdev_priv(net_dev);
1127 void __iomem *ioaddr = sis_priv->ioaddr;
1130 sis_priv->tx_full = 0;
1131 sis_priv->dirty_tx = sis_priv->cur_tx = 0;
1134 sis_priv->tx_skbuff[i] = NULL;
1136 sis_priv->tx_ring[i].link = sis_priv->tx_ring_dma +
1138 sis_priv->tx_ring[i].cmdsts = 0;
1139 sis_priv->tx_ring[i].bufptr = 0;
1143 sw32(txdp, sis_priv->tx_ring_dma);
1144 if (netif_msg_hw(sis_priv))
1160 struct sis900_private *sis_priv = netdev_priv(net_dev);
1161 void __iomem *ioaddr = sis_priv->ioaddr;
1164 sis_priv->cur_rx = 0;
1165 sis_priv->dirty_rx = 0;
1169 sis_priv->rx_skbuff[i] = NULL;
1171 sis_priv->rx_ring[i].link = sis_priv->rx_ring_dma +
1173 sis_priv->rx_ring[i].cmdsts = 0;
1174 sis_priv->rx_ring[i].bufptr = 0;
1188 sis_priv->rx_skbuff[i] = skb;
1189 sis_priv->rx_ring[i].cmdsts = RX_BUF_SIZE;
1190 sis_priv->rx_ring[i].bufptr = dma_map_single(&sis_priv->pci_dev->dev,
1194 if (unlikely(dma_mapping_error(&sis_priv->pci_dev->dev,
1195 sis_priv->rx_ring[i].bufptr))) {
1197 sis_priv->rx_skbuff[i] = NULL;
1201 sis_priv->dirty_rx = (unsigned int) (i - NUM_RX_DESC);
1204 sw32(rxdp, sis_priv->rx_ring_dma);
1205 if (netif_msg_hw(sis_priv))
1239 struct sis900_private *sis_priv = netdev_priv(net_dev);
1248 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1249 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1253 sis_priv->cur_phy, MII_RESV)) >> 3;
1275 (sis_priv->host_bridge_rev == SIS630B0 ||
1276 sis_priv->host_bridge_rev == SIS630B1)) {
1283 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1286 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV, reg14h);
1288 reg14h = mdio_read(net_dev, sis_priv->cur_phy, MII_RESV);
1290 (sis_priv->host_bridge_rev == SIS630B0 ||
1291 sis_priv->host_bridge_rev == SIS630B1))
1292 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1295 mdio_write(net_dev, sis_priv->cur_phy, MII_RESV,
1310 struct sis900_private *sis_priv = from_timer(sis_priv, t, timer);
1311 struct net_device *net_dev = sis_priv->mii_info.dev;
1312 struct mii_phy *mii_phy = sis_priv->mii;
1317 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1318 status = mdio_read(net_dev, sis_priv->cur_phy, MII_STATUS);
1325 mii_phy = sis_priv->mii;
1332 sis900_set_mode(sis_priv, speed, duplex);
1333 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1341 if(netif_msg_link(sis_priv))
1347 sis900_reset_phy(net_dev, sis_priv->cur_phy);
1349 sis630_set_eq(net_dev, sis_priv->chipset_rev);
1355 sis_priv->timer.expires = jiffies + next_tick;
1356 add_timer(&sis_priv->timer);
1373 struct sis900_private *sis_priv = netdev_priv(net_dev);
1374 void __iomem *ioaddr = sis_priv->ioaddr;
1380 sis900_auto_negotiate(net_dev, sis_priv->cur_phy);
1385 sis900_set_mode(sis_priv, speed, duplex);
1386 sis_priv->autong_complete = 1;
1453 struct sis900_private *sis_priv = netdev_priv(net_dev);
1461 if(netif_msg_link(sis_priv))
1463 sis_priv->autong_complete = 1;
1471 sis_priv->autong_complete = 0;
1488 struct sis900_private *sis_priv = netdev_priv(net_dev);
1489 struct mii_phy *phy = sis_priv->mii;
1490 int phy_addr = sis_priv->cur_phy;
1514 sis_priv->autong_complete = 1;
1524 if(netif_msg_link(sis_priv))
1544 struct sis900_private *sis_priv = netdev_priv(net_dev);
1545 void __iomem *ioaddr = sis_priv->ioaddr;
1549 if (netif_msg_tx_err(sis_priv)) {
1558 spin_lock_irqsave(&sis_priv->lock, flags);
1561 sis_priv->dirty_tx = sis_priv->cur_tx = 0;
1563 struct sk_buff *skb = sis_priv->tx_skbuff[i];
1566 dma_unmap_single(&sis_priv->pci_dev->dev,
1567 sis_priv->tx_ring[i].bufptr,
1570 sis_priv->tx_skbuff[i] = NULL;
1571 sis_priv->tx_ring[i].cmdsts = 0;
1572 sis_priv->tx_ring[i].bufptr = 0;
1576 sis_priv->tx_full = 0;
1579 spin_unlock_irqrestore(&sis_priv->lock, flags);
1584 sw32(txdp, sis_priv->tx_ring_dma);
1603 struct sis900_private *sis_priv = netdev_priv(net_dev);
1604 void __iomem *ioaddr = sis_priv->ioaddr;
1610 spin_lock_irqsave(&sis_priv->lock, flags);
1613 entry = sis_priv->cur_tx % NUM_TX_DESC;
1614 sis_priv->tx_skbuff[entry] = skb;
1617 sis_priv->tx_ring[entry].bufptr = dma_map_single(&sis_priv->pci_dev->dev,
1620 if (unlikely(dma_mapping_error(&sis_priv->pci_dev->dev,
1621 sis_priv->tx_ring[entry].bufptr))) {
1623 sis_priv->tx_skbuff[entry] = NULL;
1625 spin_unlock_irqrestore(&sis_priv->lock, flags);
1628 sis_priv->tx_ring[entry].cmdsts = (OWN | INTR | skb->len);
1631 sis_priv->cur_tx ++;
1632 index_cur_tx = sis_priv->cur_tx;
1633 index_dirty_tx = sis_priv->dirty_tx;
1640 sis_priv->tx_full = 1;
1647 sis_priv->tx_full = 1;
1651 spin_unlock_irqrestore(&sis_priv->lock, flags);
1653 if (netif_msg_tx_queued(sis_priv))
1673 struct sis900_private *sis_priv = netdev_priv(net_dev);
1675 void __iomem *ioaddr = sis_priv->ioaddr;
1679 spin_lock (&sis_priv->lock);
1700 if(netif_msg_intr(sis_priv))
1706 if(netif_msg_intr(sis_priv))
1714 if(netif_msg_intr(sis_priv))
1719 spin_unlock (&sis_priv->lock);
1735 struct sis900_private *sis_priv = netdev_priv(net_dev);
1736 void __iomem *ioaddr = sis_priv->ioaddr;
1737 unsigned int entry = sis_priv->cur_rx % NUM_RX_DESC;
1738 u32 rx_status = sis_priv->rx_ring[entry].cmdsts;
1741 if (netif_msg_rx_status(sis_priv))
1744 sis_priv->cur_rx, sis_priv->dirty_rx, rx_status);
1745 rx_work_limit = sis_priv->dirty_rx + NUM_RX_DESC - sis_priv->cur_rx;
1765 if (netif_msg_rx_err(sis_priv))
1779 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1784 dma_unmap_single(&sis_priv->pci_dev->dev,
1785 sis_priv->rx_ring[entry].bufptr,
1797 skb = sis_priv->rx_skbuff[entry];
1805 if (sis_priv->rx_skbuff[entry] == NULL) {
1806 if (netif_msg_rx_err(sis_priv))
1810 net_dev->name, sis_priv->cur_rx,
1811 sis_priv->dirty_rx);
1817 rx_skb = sis_priv->rx_skbuff[entry];
1827 sis_priv->dirty_rx++;
1829 sis_priv->rx_skbuff[entry] = skb;
1830 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1831 sis_priv->rx_ring[entry].bufptr =
1832 dma_map_single(&sis_priv->pci_dev->dev,
1835 if (unlikely(dma_mapping_error(&sis_priv->pci_dev->dev,
1836 sis_priv->rx_ring[entry].bufptr))) {
1838 sis_priv->rx_skbuff[entry] = NULL;
1842 sis_priv->cur_rx++;
1843 entry = sis_priv->cur_rx % NUM_RX_DESC;
1844 rx_status = sis_priv->rx_ring[entry].cmdsts;
1849 for (; sis_priv->cur_rx != sis_priv->dirty_rx; sis_priv->dirty_rx++) {
1852 entry = sis_priv->dirty_rx % NUM_RX_DESC;
1854 if (sis_priv->rx_skbuff[entry] == NULL) {
1864 sis_priv->rx_skbuff[entry] = skb;
1865 sis_priv->rx_ring[entry].cmdsts = RX_BUF_SIZE;
1866 sis_priv->rx_ring[entry].bufptr =
1867 dma_map_single(&sis_priv->pci_dev->dev,
1870 if (unlikely(dma_mapping_error(&sis_priv->pci_dev->dev,
1871 sis_priv->rx_ring[entry].bufptr))) {
1873 sis_priv->rx_skbuff[entry] = NULL;
1896 struct sis900_private *sis_priv = netdev_priv(net_dev);
1898 for (; sis_priv->dirty_tx != sis_priv->cur_tx; sis_priv->dirty_tx++) {
1903 entry = sis_priv->dirty_tx % NUM_TX_DESC;
1904 tx_status = sis_priv->tx_ring[entry].cmdsts;
1915 if (netif_msg_tx_err(sis_priv))
1935 skb = sis_priv->tx_skbuff[entry];
1936 dma_unmap_single(&sis_priv->pci_dev->dev,
1937 sis_priv->tx_ring[entry].bufptr, skb->len,
1940 sis_priv->tx_skbuff[entry] = NULL;
1941 sis_priv->tx_ring[entry].bufptr = 0;
1942 sis_priv->tx_ring[entry].cmdsts = 0;
1945 if (sis_priv->tx_full && netif_queue_stopped(net_dev) &&
1946 sis_priv->cur_tx - sis_priv->dirty_tx < NUM_TX_DESC - 4) {
1949 sis_priv->tx_full = 0;
1964 struct sis900_private *sis_priv = netdev_priv(net_dev);
1965 struct pci_dev *pdev = sis_priv->pci_dev;
1966 void __iomem *ioaddr = sis_priv->ioaddr;
1979 del_timer(&sis_priv->timer);
1985 skb = sis_priv->rx_skbuff[i];
1988 sis_priv->rx_ring[i].bufptr,
1991 sis_priv->rx_skbuff[i] = NULL;
1995 skb = sis_priv->tx_skbuff[i];
1998 sis_priv->tx_ring[i].bufptr,
2001 sis_priv->tx_skbuff[i] = NULL;
2021 struct sis900_private *sis_priv = netdev_priv(net_dev);
2025 strlcpy(info->bus_info, pci_name(sis_priv->pci_dev),
2031 struct sis900_private *sis_priv = netdev_priv(net_dev);
2032 return sis_priv->msg_enable;
2037 struct sis900_private *sis_priv = netdev_priv(net_dev);
2038 sis_priv->msg_enable = value;
2043 struct sis900_private *sis_priv = netdev_priv(net_dev);
2044 return mii_link_ok(&sis_priv->mii_info);
2050 struct sis900_private *sis_priv = netdev_priv(net_dev);
2051 spin_lock_irq(&sis_priv->lock);
2052 mii_ethtool_get_link_ksettings(&sis_priv->mii_info, cmd);
2053 spin_unlock_irq(&sis_priv->lock);
2060 struct sis900_private *sis_priv = netdev_priv(net_dev);
2062 spin_lock_irq(&sis_priv->lock);
2063 rt = mii_ethtool_set_link_ksettings(&sis_priv->mii_info, cmd);
2064 spin_unlock_irq(&sis_priv->lock);
2070 struct sis900_private *sis_priv = netdev_priv(net_dev);
2071 return mii_nway_restart(&sis_priv->mii_info);
2087 struct sis900_private *sis_priv = netdev_priv(net_dev);
2088 void __iomem *ioaddr = sis_priv->ioaddr;
2092 pci_read_config_dword(sis_priv->pci_dev, CFGPMCSR, &cfgpmcsr);
2094 pci_write_config_dword(sis_priv->pci_dev, CFGPMCSR, cfgpmcsr);
2096 if (netif_msg_wol(sis_priv))
2112 pci_read_config_dword(sis_priv->pci_dev, CFGPMCSR, &cfgpmcsr);
2114 pci_write_config_dword(sis_priv->pci_dev, CFGPMCSR, cfgpmcsr);
2115 if (netif_msg_wol(sis_priv))
2138 struct sis900_private *sis_priv = netdev_priv(dev);
2140 return sis_priv->eeprom_size;
2145 struct sis900_private *sis_priv = netdev_priv(net_dev);
2146 void __iomem *ioaddr = sis_priv->ioaddr;
2152 if (sis_priv->chipset_rev == SIS96x_900_REV) {
2157 for (i = 0; i < sis_priv->eeprom_size / 2; i++)
2169 for (i = 0; i < sis_priv->eeprom_size / 2; i++)
2180 struct sis900_private *sis_priv = netdev_priv(dev);
2184 eebuf = kmalloc(sis_priv->eeprom_size, GFP_KERNEL);
2189 spin_lock_irq(&sis_priv->lock);
2191 spin_unlock_irq(&sis_priv->lock);
2223 struct sis900_private *sis_priv = netdev_priv(net_dev);
2228 data->phy_id = sis_priv->mii->phy_addr;
2255 struct sis900_private *sis_priv = netdev_priv(dev);
2256 struct mii_phy *mii_phy = sis_priv->mii;
2376 struct sis900_private *sis_priv = netdev_priv(net_dev);
2377 void __iomem *ioaddr = sis_priv->ioaddr;
2383 if((sis_priv->chipset_rev >= SIS635A_900_REV) ||
2384 (sis_priv->chipset_rev == SIS900B_900_REV))
2411 sis_priv->chipset_rev);
2451 struct sis900_private *sis_priv = netdev_priv(net_dev);
2452 void __iomem *ioaddr = sis_priv->ioaddr;
2466 if (sis_priv->chipset_rev >= SIS635A_900_REV ||
2467 sis_priv->chipset_rev == SIS900B_900_REV)
2483 struct sis900_private *sis_priv = netdev_priv(net_dev);
2487 while (sis_priv->first_mii) {
2488 struct mii_phy *phy = sis_priv->first_mii;
2490 sis_priv->first_mii = phy->next;
2494 dma_free_coherent(&pci_dev->dev, RX_TOTAL_SIZE, sis_priv->rx_ring,
2495 sis_priv->rx_ring_dma);
2496 dma_free_coherent(&pci_dev->dev, TX_TOTAL_SIZE, sis_priv->tx_ring,
2497 sis_priv->tx_ring_dma);
2498 pci_iounmap(pci_dev, sis_priv->ioaddr);
2505 struct sis900_private *sis_priv = netdev_priv(net_dev);
2506 void __iomem *ioaddr = sis_priv->ioaddr;
2523 struct sis900_private *sis_priv = netdev_priv(net_dev);
2524 void __iomem *ioaddr = sis_priv->ioaddr;
2540 sis900_set_mode(sis_priv, HW_SPEED_10_MBPS, FDX_CAPABLE_HALF_SELECTED);
2547 sis900_check_mode(net_dev, sis_priv->mii);