Lines Matching refs:eth
109 mace->eth.mac_addr = macaddr;
116 while ((___rval = mace->eth.phy_data) & MDIO_BUSY) { \
124 mace->eth.phy_regs = (priv->phy_addr << 5) | (phyreg & 0x1f);
126 mace->eth.phy_trans_go = 1;
195 mace->eth.mac_ctrl = priv->mac_ctrl;
204 mace->eth.mac_ctrl = priv->mac_ctrl;
218 mace->eth.tx_ring_base = priv->tx_ring_dma;
239 mace->eth.rx_fifo = priv->rx_ring_dmas[i];
276 mace->eth.mac_ctrl = SGI_MAC_RESET;
278 mace->eth.mac_ctrl = 0;
295 mace->eth.mac_ctrl = priv->mac_ctrl;
303 mace->eth.dma_ctrl = priv->dma_ctrl;
342 mace->eth.dma_ctrl = priv->dma_ctrl;
366 mace->eth.dma_ctrl = priv->dma_ctrl;
386 mace->eth.dma_ctrl = priv->dma_ctrl;
458 mace->eth.rx_fifo = priv->rx_ring_dmas[priv->rx_write];
464 mace->eth.dma_ctrl = priv->dma_ctrl;
465 mace->eth.int_stat = METH_INT_RX_THRESHOLD;
487 mace->eth.dma_ctrl = priv->dma_ctrl;
535 mace->eth.int_stat = METH_INT_TX_EMPTY | METH_INT_TX_PKT;
558 mace->eth.int_stat = METH_INT_RX_UNDERFLOW;
563 mace->eth.dma_ctrl = priv->dma_ctrl;
567 mace->eth.int_stat = METH_INT_ERROR;
579 status = mace->eth.int_stat;
598 status = mace->eth.int_stat;
692 mace->eth.tx_info = priv->tx_write;
707 mace->eth.dma_ctrl = priv->dma_ctrl;
720 mace->eth.dma_ctrl = priv->dma_ctrl;
753 mace->eth.dma_ctrl = priv->dma_ctrl;
803 mace->eth.mac_ctrl = priv->mac_ctrl;
804 mace->eth.mcast_filter = priv->mcast_filter;
838 dev->base_addr = (unsigned long)&mace->eth;
853 dev->name, (unsigned int)(mace->eth.mac_ctrl >> 29));