Lines Matching refs:value
240 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
401 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
488 #define TD_MSS_MAX 0x07ffu /* MSS value */
844 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
847 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
854 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
868 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
871 tp->ocp_base = value << 4;
875 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
888 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
890 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
902 int value;
906 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
915 return value;
932 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
935 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
962 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
966 r8169_mdio_write(tp, reg, value);
973 int value;
981 value = r8169_mdio_read(tp, reg);
985 return value;
1027 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1029 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
2623 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2627 RTL_W32(tp, CSIDR, value);
2650 /* According to Realtek the value at config space address 0x070f
5130 u32 value = rtl_eri_read(tp, 0xe0);
5132 mac_addr[0] = (value >> 0) & 0xff;
5133 mac_addr[1] = (value >> 8) & 0xff;
5134 mac_addr[2] = (value >> 16) & 0xff;
5135 mac_addr[3] = (value >> 24) & 0xff;
5137 value = rtl_eri_read(tp, 0xe4);
5138 mac_addr[4] = (value >> 0) & 0xff;
5139 mac_addr[5] = (value >> 8) & 0xff;