Lines Matching refs:tp
80 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
81 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
82 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
83 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
84 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
85 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
638 typedef void (*rtl_generic_fct)(struct rtl8169_private *tp);
667 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
669 return &tp->pci_dev->dev;
672 static void rtl_lock_config_regs(struct rtl8169_private *tp)
674 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
677 static void rtl_unlock_config_regs(struct rtl8169_private *tp)
679 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
682 static void rtl_pci_commit(struct rtl8169_private *tp)
685 RTL_R8(tp, ChipCmd);
688 static bool rtl_is_8125(struct rtl8169_private *tp)
690 return tp->mac_version >= RTL_GIGA_MAC_VER_60;
693 static bool rtl_is_8168evl_up(struct rtl8169_private *tp)
695 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
696 tp->mac_version != RTL_GIGA_MAC_VER_39 &&
697 tp->mac_version <= RTL_GIGA_MAC_VER_52;
700 static bool rtl_supports_eee(struct rtl8169_private *tp)
702 return tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
703 tp->mac_version != RTL_GIGA_MAC_VER_37 &&
704 tp->mac_version != RTL_GIGA_MAC_VER_39;
728 static void rtl_read_mac_from_reg(struct rtl8169_private *tp, u8 *mac, int reg)
733 mac[i] = RTL_R8(tp, reg + i);
741 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
747 if (c->check(tp) == high)
753 netdev_err(tp->dev, "%s == %d (loop: %d, delay: %lu).\n",
758 static bool rtl_loop_wait_high(struct rtl8169_private *tp,
762 return rtl_loop_wait(tp, c, d, n, true);
765 static bool rtl_loop_wait_low(struct rtl8169_private *tp,
769 return rtl_loop_wait(tp, c, d, n, false);
780 static bool name ## _check(struct rtl8169_private *tp)
782 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
786 netdev_err(tp->dev, "Invalid ocp reg %x!\n", reg);
794 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
797 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
799 if (rtl_ocp_reg_failure(tp, reg))
802 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
804 rtl_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
807 static int r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
809 if (rtl_ocp_reg_failure(tp, reg))
812 RTL_W32(tp, GPHY_OCP, reg << 15);
814 return rtl_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
815 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT;
818 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
820 if (rtl_ocp_reg_failure(tp, reg))
823 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
826 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
828 if (rtl_ocp_reg_failure(tp, reg))
831 RTL_W32(tp, OCPDR, reg << 15);
833 return RTL_R32(tp, OCPDR);
836 static void r8168_mac_ocp_modify(struct rtl8169_private *tp, u32 reg, u16 mask,
839 u16 data = r8168_mac_ocp_read(tp, reg);
841 r8168_mac_ocp_write(tp, reg, (data & ~mask) | set);
844 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
847 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
851 if (tp->ocp_base != OCP_STD_PHY_BASE)
854 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
857 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
860 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4;
862 if (tp->ocp_base != OCP_STD_PHY_BASE)
865 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
868 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
871 tp->ocp_base = value << 4;
875 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
878 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
880 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
885 return RTL_R32(tp, PHYAR) & 0x80000000;
888 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
890 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
892 rtl_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
900 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
904 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
906 value = rtl_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
907 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT;
920 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
923 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
925 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
926 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
927 RTL_W32(tp, EPHY_RXER_NUM, 0);
929 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
932 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
934 r8168dp_1_mdio_access(tp, reg,
938 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
940 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
943 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
944 RTL_W32(tp, EPHY_RXER_NUM, 0);
946 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
947 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : -ETIMEDOUT;
952 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
954 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
957 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
959 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
962 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
964 r8168dp_2_mdio_start(tp);
966 r8169_mdio_write(tp, reg, value);
968 r8168dp_2_mdio_stop(tp);
971 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
979 r8168dp_2_mdio_start(tp);
981 value = r8169_mdio_read(tp, reg);
983 r8168dp_2_mdio_stop(tp);
988 static void rtl_writephy(struct rtl8169_private *tp, int location, int val)
990 switch (tp->mac_version) {
992 r8168dp_1_mdio_write(tp, location, val);
996 r8168dp_2_mdio_write(tp, location, val);
999 r8168g_mdio_write(tp, location, val);
1002 r8169_mdio_write(tp, location, val);
1007 static int rtl_readphy(struct rtl8169_private *tp, int location)
1009 switch (tp->mac_version) {
1011 return r8168dp_1_mdio_read(tp, location);
1014 return r8168dp_2_mdio_read(tp, location);
1016 return r8168g_mdio_read(tp, location);
1018 return r8169_mdio_read(tp, location);
1024 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1027 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1029 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1032 rtl_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1037 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1039 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1041 return rtl_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1042 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1045 static void r8168fp_adjust_ocp_cmd(struct rtl8169_private *tp, u32 *cmd, int type)
1048 if (tp->mac_version == RTL_GIGA_MAC_VER_52 && type == ERIAR_OOB)
1054 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1057 static void _rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1063 RTL_W32(tp, ERIDR, val);
1064 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1065 RTL_W32(tp, ERIAR, cmd);
1067 rtl_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1070 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1073 _rtl_eri_write(tp, addr, mask, val, ERIAR_EXGMAC);
1076 static u32 _rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1080 r8168fp_adjust_ocp_cmd(tp, &cmd, type);
1081 RTL_W32(tp, ERIAR, cmd);
1083 return rtl_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1084 RTL_R32(tp, ERIDR) : ~0;
1087 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr)
1089 return _rtl_eri_read(tp, addr, ERIAR_EXGMAC);
1092 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 p, u32 m)
1094 u32 val = rtl_eri_read(tp, addr);
1096 rtl_eri_write(tp, addr, ERIAR_MASK_1111, (val & ~m) | p);
1099 static void rtl_eri_set_bits(struct rtl8169_private *tp, int addr, u32 p)
1101 rtl_w0w1_eri(tp, addr, p, 0);
1104 static void rtl_eri_clear_bits(struct rtl8169_private *tp, int addr, u32 m)
1106 rtl_w0w1_eri(tp, addr, 0, m);
1109 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u16 reg)
1111 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff));
1112 return rtl_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1113 RTL_R32(tp, OCPDR) : ~0;
1116 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u16 reg)
1118 return _rtl_eri_read(tp, reg, ERIAR_OOB);
1121 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1124 RTL_W32(tp, OCPDR, data);
1125 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1126 rtl_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1129 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1132 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1136 static void r8168dp_oob_notify(struct rtl8169_private *tp, u8 cmd)
1138 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd);
1140 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001);
1147 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1149 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1156 reg = rtl8168_get_ocp_reg(tp);
1158 return r8168dp_ocp_read(tp, reg) & 0x00000800;
1163 return r8168ep_ocp_read(tp, 0x124) & 0x00000001;
1168 return RTL_R8(tp, IBISR0) & 0x20;
1171 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1173 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1174 rtl_loop_wait_high(tp, &rtl_ocp_tx_cond, 50000, 2000);
1175 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1176 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1179 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1181 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_START);
1182 rtl_loop_wait_high(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1185 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1187 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1188 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1189 rtl_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1192 static void rtl8168_driver_start(struct rtl8169_private *tp)
1194 switch (tp->mac_version) {
1198 rtl8168dp_driver_start(tp);
1201 rtl8168ep_driver_start(tp);
1209 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1211 r8168dp_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1212 rtl_loop_wait_low(tp, &rtl_dp_ocp_read_cond, 10000, 10);
1215 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1217 rtl8168ep_stop_cmac(tp);
1218 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1219 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01);
1220 rtl_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10000, 10);
1223 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1225 switch (tp->mac_version) {
1229 rtl8168dp_driver_stop(tp);
1232 rtl8168ep_driver_stop(tp);
1240 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1242 u16 reg = rtl8168_get_ocp_reg(tp);
1244 return !!(r8168dp_ocp_read(tp, reg) & 0x00008000);
1247 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1249 return r8168ep_ocp_read(tp, 0x128) & 0x00000001;
1252 static bool r8168_check_dash(struct rtl8169_private *tp)
1254 switch (tp->mac_version) {
1258 return r8168dp_check_dash(tp);
1260 return r8168ep_check_dash(tp);
1266 static void rtl_reset_packet_filter(struct rtl8169_private *tp)
1268 rtl_eri_clear_bits(tp, 0xdc, BIT(0));
1269 rtl_eri_set_bits(tp, 0xdc, BIT(0));
1274 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1277 u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1279 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1281 return rtl_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1282 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1285 static u32 rtl_get_events(struct rtl8169_private *tp)
1287 if (rtl_is_8125(tp))
1288 return RTL_R32(tp, IntrStatus_8125);
1290 return RTL_R16(tp, IntrStatus);
1293 static void rtl_ack_events(struct rtl8169_private *tp, u32 bits)
1295 if (rtl_is_8125(tp))
1296 RTL_W32(tp, IntrStatus_8125, bits);
1298 RTL_W16(tp, IntrStatus, bits);
1301 static void rtl_irq_disable(struct rtl8169_private *tp)
1303 if (rtl_is_8125(tp))
1304 RTL_W32(tp, IntrMask_8125, 0);
1306 RTL_W16(tp, IntrMask, 0);
1309 static void rtl_irq_enable(struct rtl8169_private *tp)
1311 if (rtl_is_8125(tp))
1312 RTL_W32(tp, IntrMask_8125, tp->irq_mask);
1314 RTL_W16(tp, IntrMask, tp->irq_mask);
1317 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1319 rtl_irq_disable(tp);
1320 rtl_ack_events(tp, 0xffffffff);
1321 rtl_pci_commit(tp);
1324 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1326 struct phy_device *phydev = tp->phydev;
1328 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1329 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1331 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1332 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1334 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1335 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1337 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1338 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1340 rtl_reset_packet_filter(tp);
1341 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1342 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1344 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011);
1345 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005);
1347 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f);
1348 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f);
1350 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1352 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02);
1353 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a);
1355 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
1364 struct rtl8169_private *tp = netdev_priv(dev);
1367 wol->wolopts = tp->saved_wolopts;
1370 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1387 rtl_unlock_config_regs(tp);
1389 if (rtl_is_8168evl_up(tp)) {
1392 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2);
1394 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2);
1395 } else if (rtl_is_8125(tp)) {
1398 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0));
1400 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0);
1404 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1407 RTL_W8(tp, cfg[i].reg, options);
1410 switch (tp->mac_version) {
1412 options = RTL_R8(tp, Config1) & ~PMEnable;
1415 RTL_W8(tp, Config1, options);
1420 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1423 RTL_W8(tp, Config2, options);
1429 rtl_lock_config_regs(tp);
1431 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1432 tp->dev->wol_enabled = wolopts ? 1 : 0;
1437 struct rtl8169_private *tp = netdev_priv(dev);
1442 tp->saved_wolopts = wol->wolopts;
1443 __rtl8169_set_wol(tp, tp->saved_wolopts);
1451 struct rtl8169_private *tp = netdev_priv(dev);
1452 struct rtl_fw *rtl_fw = tp->rtl_fw;
1455 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1470 struct rtl8169_private *tp = netdev_priv(dev);
1476 tp->mac_version > RTL_GIGA_MAC_VER_06)
1482 static void rtl_set_rx_config_features(struct rtl8169_private *tp,
1485 u32 rx_config = RTL_R32(tp, RxConfig);
1492 if (rtl_is_8125(tp)) {
1499 RTL_W32(tp, RxConfig, rx_config);
1505 struct rtl8169_private *tp = netdev_priv(dev);
1507 rtl_set_rx_config_features(tp, features);
1510 tp->cp_cmd |= RxChkSum;
1512 tp->cp_cmd &= ~RxChkSum;
1514 if (!rtl_is_8125(tp)) {
1516 tp->cp_cmd |= RxVlan;
1518 tp->cp_cmd &= ~RxVlan;
1521 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1522 rtl_pci_commit(tp);
1544 struct rtl8169_private *tp = netdev_priv(dev);
1545 u32 __iomem *data = tp->mmio_addr;
1581 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1584 static void rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1586 dma_addr_t paddr = tp->counters_phys_addr;
1589 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1590 rtl_pci_commit(tp);
1592 RTL_W32(tp, CounterAddrLow, cmd);
1593 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1595 rtl_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1598 static void rtl8169_reset_counters(struct rtl8169_private *tp)
1604 if (tp->mac_version >= RTL_GIGA_MAC_VER_19)
1605 rtl8169_do_counters(tp, CounterReset);
1608 static void rtl8169_update_counters(struct rtl8169_private *tp)
1610 u8 val = RTL_R8(tp, ChipCmd);
1617 rtl8169_do_counters(tp, CounterDump);
1620 static void rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1622 struct rtl8169_counters *counters = tp->counters;
1639 if (tp->tc_offset.inited)
1642 rtl8169_reset_counters(tp);
1643 rtl8169_update_counters(tp);
1645 tp->tc_offset.tx_errors = counters->tx_errors;
1646 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1647 tp->tc_offset.tx_aborted = counters->tx_aborted;
1648 tp->tc_offset.rx_missed = counters->rx_missed;
1649 tp->tc_offset.inited = true;
1655 struct rtl8169_private *tp = netdev_priv(dev);
1658 counters = tp->counters;
1659 rtl8169_update_counters(tp);
1739 rtl_coalesce_info(struct rtl8169_private *tp)
1743 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1749 if (tp->phydev->speed == SPEED_UNKNOWN)
1753 if (tp->phydev->speed == ci->speed)
1762 struct rtl8169_private *tp = netdev_priv(dev);
1767 if (rtl_is_8125(tp))
1773 ci = rtl_coalesce_info(tp);
1777 scale = ci->scale_nsecs[tp->cp_cmd & INTT_MASK];
1779 intrmit = RTL_R16(tp, IntrMitigate);
1798 static int rtl_coalesce_choose_scale(struct rtl8169_private *tp, u32 usec,
1804 ci = rtl_coalesce_info(tp);
1820 struct rtl8169_private *tp = netdev_priv(dev);
1827 if (rtl_is_8125(tp))
1834 scale = rtl_coalesce_choose_scale(tp, coal_usec_max, &cp01);
1866 RTL_W16(tp, IntrMitigate, w);
1869 if (rtl_is_8168evl_up(tp)) {
1872 tp->cp_cmd |= PktCntrDisable;
1874 tp->cp_cmd &= ~PktCntrDisable;
1877 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
1878 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1879 rtl_pci_commit(tp);
1886 struct rtl8169_private *tp = netdev_priv(dev);
1888 if (!rtl_supports_eee(tp))
1891 return phy_ethtool_get_eee(tp->phydev, data);
1896 struct rtl8169_private *tp = netdev_priv(dev);
1899 if (!rtl_supports_eee(tp))
1902 ret = phy_ethtool_set_eee(tp->phydev, data);
1905 tp->eee_adv = phy_read_mmd(dev->phydev, MDIO_MMD_AN,
1932 static void rtl_enable_eee(struct rtl8169_private *tp)
1934 struct phy_device *phydev = tp->phydev;
1938 if (tp->eee_adv >= 0)
1939 adv = tp->eee_adv;
1954 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1958 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2072 static void rtl_release_firmware(struct rtl8169_private *tp)
2074 if (tp->rtl_fw) {
2075 rtl_fw_release_firmware(tp->rtl_fw);
2076 kfree(tp->rtl_fw);
2077 tp->rtl_fw = NULL;
2081 void r8169_apply_firmware(struct rtl8169_private *tp)
2086 if (tp->rtl_fw) {
2087 rtl_fw_write_firmware(tp, tp->rtl_fw);
2088 /* At least one firmware doesn't reset tp->ocp_base. */
2089 tp->ocp_base = OCP_STD_PHY_BASE;
2092 phy_read_poll_timeout(tp->phydev, MII_BMCR, val,
2098 static void rtl8168_config_eee_mac(struct rtl8169_private *tp)
2101 if (tp->mac_version != RTL_GIGA_MAC_VER_38)
2102 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
2104 rtl_eri_set_bits(tp, 0x1b0, 0x0003);
2107 static void rtl8125a_config_eee_mac(struct rtl8169_private *tp)
2109 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2110 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1));
2113 static void rtl8125_set_eee_txidle_timer(struct rtl8169_private *tp)
2115 RTL_W16(tp, EEE_TXIDLE_TIMER_8125, tp->dev->mtu + ETH_HLEN + 0x20);
2118 static void rtl8125b_config_eee_mac(struct rtl8169_private *tp)
2120 rtl8125_set_eee_txidle_timer(tp);
2121 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0));
2124 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
2132 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, w[0] | (w[1] << 16));
2133 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, w[2]);
2134 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, w[0] << 16);
2135 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, w[1] | (w[2] << 16));
2138 u16 rtl8168h_2_get_adc_bias_ioffset(struct rtl8169_private *tp)
2142 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
2143 data1 = r8168_mac_ocp_read(tp, 0xdd02);
2144 data2 = r8168_mac_ocp_read(tp, 0xdd00);
2154 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
2156 set_bit(flag, tp->wk.flags);
2157 schedule_work(&tp->wk.work);
2160 static void rtl8169_init_phy(struct rtl8169_private *tp)
2162 r8169_hw_phy_config(tp, tp->phydev, tp->mac_version);
2164 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2165 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2166 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2168 RTL_W8(tp, 0x82, 0x01);
2171 if (tp->mac_version == RTL_GIGA_MAC_VER_05 &&
2172 tp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_GIGABYTE &&
2173 tp->pci_dev->subsystem_device == 0xe000)
2174 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b);
2177 phy_speed_up(tp->phydev);
2179 if (rtl_supports_eee(tp))
2180 rtl_enable_eee(tp);
2182 genphy_soft_reset(tp->phydev);
2185 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2187 rtl_unlock_config_regs(tp);
2189 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
2190 rtl_pci_commit(tp);
2192 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
2193 rtl_pci_commit(tp);
2195 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
2196 rtl_rar_exgmac_set(tp, addr);
2198 rtl_lock_config_regs(tp);
2203 struct rtl8169_private *tp = netdev_priv(dev);
2210 rtl_rar_set(tp, dev->dev_addr);
2215 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
2217 switch (tp->mac_version) {
2226 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
2234 static void rtl_pll_power_down(struct rtl8169_private *tp)
2236 if (r8168_check_dash(tp))
2239 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
2240 tp->mac_version == RTL_GIGA_MAC_VER_33)
2241 rtl_ephy_write(tp, 0x19, 0xff64);
2243 if (device_may_wakeup(tp_to_dev(tp))) {
2244 phy_speed_down(tp->phydev, false);
2245 rtl_wol_suspend_quirk(tp);
2249 switch (tp->mac_version) {
2262 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
2267 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000);
2268 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
2275 static void rtl_pll_power_up(struct rtl8169_private *tp)
2277 switch (tp->mac_version) {
2284 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
2292 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2297 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
2298 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000);
2304 phy_resume(tp->phydev);
2307 static void rtl_init_rxcfg(struct rtl8169_private *tp)
2309 switch (tp->mac_version) {
2312 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
2317 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
2320 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
2323 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST);
2326 RTL_W32(tp, RxConfig, RX_FETCH_DFLT_8125 | RX_DMA_BURST |
2330 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
2335 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
2337 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
2340 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
2342 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2343 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
2346 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
2348 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2349 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
2352 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
2354 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2357 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
2359 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2362 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
2364 RTL_W8(tp, MaxTxPacketSize, 0x24);
2365 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
2366 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
2369 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
2371 RTL_W8(tp, MaxTxPacketSize, 0x3f);
2372 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
2373 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
2376 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
2378 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
2381 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
2383 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
2386 static void rtl_jumbo_config(struct rtl8169_private *tp)
2388 bool jumbo = tp->dev->mtu > ETH_DATA_LEN;
2391 rtl_unlock_config_regs(tp);
2392 switch (tp->mac_version) {
2397 r8168b_1_hw_jumbo_enable(tp);
2399 r8168b_1_hw_jumbo_disable(tp);
2405 r8168c_hw_jumbo_enable(tp);
2407 r8168c_hw_jumbo_disable(tp);
2412 r8168dp_hw_jumbo_enable(tp);
2414 r8168dp_hw_jumbo_disable(tp);
2418 pcie_set_readrq(tp->pci_dev, 512);
2419 r8168e_hw_jumbo_enable(tp);
2421 r8168e_hw_jumbo_disable(tp);
2427 rtl_lock_config_regs(tp);
2429 if (pci_is_pcie(tp->pci_dev) && tp->supports_gmii)
2430 pcie_set_readrq(tp->pci_dev, readrq);
2434 tp->phydev->advertising, !jumbo);
2436 tp->phydev->advertising, !jumbo);
2437 phy_start_aneg(tp->phydev);
2442 return RTL_R8(tp, ChipCmd) & CmdReset;
2445 static void rtl_hw_reset(struct rtl8169_private *tp)
2447 RTL_W8(tp, ChipCmd, CmdReset);
2449 rtl_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
2452 static void rtl_request_firmware(struct rtl8169_private *tp)
2457 if (tp->rtl_fw || !tp->fw_name)
2468 rtl_fw->fw_name = tp->fw_name;
2469 rtl_fw->dev = tp_to_dev(tp);
2474 tp->rtl_fw = rtl_fw;
2477 static void rtl_rx_close(struct rtl8169_private *tp)
2479 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
2484 return RTL_R8(tp, TxPoll) & NPQ;
2489 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
2494 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
2500 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103;
2503 static void rtl_wait_txrx_fifo_empty(struct rtl8169_private *tp)
2505 switch (tp->mac_version) {
2507 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42);
2508 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2511 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2514 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
2515 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42);
2516 rtl_loop_wait_high(tp, &rtl_rxtx_empty_cond_2, 100, 42);
2523 static void rtl_enable_rxdvgate(struct rtl8169_private *tp)
2525 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
2527 rtl_wait_txrx_fifo_empty(tp);
2530 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
2535 if (rtl_is_8168evl_up(tp))
2538 RTL_W32(tp, TxConfig, val);
2541 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
2544 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
2547 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
2554 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2555 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
2556 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2557 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
2560 static void rtl8169_set_magic_reg(struct rtl8169_private *tp)
2564 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
2566 else if (tp->mac_version == RTL_GIGA_MAC_VER_06)
2571 if (RTL_R8(tp, Config2) & PCI_Clock_66MHz)
2574 RTL_W32(tp, 0x7c, val);
2582 struct rtl8169_private *tp = netdev_priv(dev);
2591 tp->mac_version == RTL_GIGA_MAC_VER_35) {
2604 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
2611 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
2612 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
2614 tmp = RTL_R32(tp, RxConfig);
2615 RTL_W32(tp, RxConfig, (tmp & ~RX_CONFIG_ACCEPT_OK_MASK) | rx_mode);
2620 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
2623 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
2625 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2627 RTL_W32(tp, CSIDR, value);
2628 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
2631 rtl_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
2634 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
2636 u32 func = PCI_FUNC(tp->pci_dev->devfn);
2638 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
2641 return rtl_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
2642 RTL_R32(tp, CSIDR) : ~0;
2645 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
2647 struct pci_dev *pdev = tp->pci_dev;
2658 netdev_notice_once(tp->dev,
2660 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
2661 rtl_csi_write(tp, 0x070c, csi | val << 24);
2664 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
2666 rtl_csi_access_enable(tp, 0x27);
2675 static void __rtl_ephy_init(struct rtl8169_private *tp,
2681 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
2682 rtl_ephy_write(tp, e->offset, w);
2687 #define rtl_ephy_init(tp, a) __rtl_ephy_init(tp, a, ARRAY_SIZE(a))
2689 static void rtl_disable_clock_request(struct rtl8169_private *tp)
2691 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
2695 static void rtl_enable_clock_request(struct rtl8169_private *tp)
2697 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
2701 static void rtl_pcie_state_l2l3_disable(struct rtl8169_private *tp)
2704 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23);
2707 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
2710 if (enable && tp->aspm_manageable) {
2711 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
2712 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
2714 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
2715 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
2721 static void rtl_set_fifo_size(struct rtl8169_private *tp, u16 rx_stat,
2727 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn);
2728 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn);
2731 static void rtl8168g_set_pause_thresholds(struct rtl8169_private *tp,
2735 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low);
2736 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high);
2739 static void rtl_hw_start_8168b(struct rtl8169_private *tp)
2741 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2744 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
2746 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
2748 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2750 rtl_disable_clock_request(tp);
2753 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
2763 rtl_set_def_aspm_entry_latency(tp);
2765 rtl_ephy_init(tp, e_info_8168cp);
2767 __rtl_hw_start_8168cp(tp);
2770 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
2772 rtl_set_def_aspm_entry_latency(tp);
2774 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2777 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
2779 rtl_set_def_aspm_entry_latency(tp);
2781 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
2784 RTL_W8(tp, DBG_REG, 0x20);
2787 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
2795 rtl_set_def_aspm_entry_latency(tp);
2797 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2799 rtl_ephy_init(tp, e_info_8168c_1);
2801 __rtl_hw_start_8168cp(tp);
2804 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
2811 rtl_set_def_aspm_entry_latency(tp);
2813 rtl_ephy_init(tp, e_info_8168c_2);
2815 __rtl_hw_start_8168cp(tp);
2818 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
2820 rtl_hw_start_8168c_2(tp);
2823 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
2825 rtl_set_def_aspm_entry_latency(tp);
2827 __rtl_hw_start_8168cp(tp);
2830 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
2832 rtl_set_def_aspm_entry_latency(tp);
2834 rtl_disable_clock_request(tp);
2837 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
2846 rtl_set_def_aspm_entry_latency(tp);
2848 rtl_ephy_init(tp, e_info_8168d_4);
2850 rtl_enable_clock_request(tp);
2853 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
2871 rtl_set_def_aspm_entry_latency(tp);
2873 rtl_ephy_init(tp, e_info_8168e_1);
2875 rtl_disable_clock_request(tp);
2878 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
2879 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
2881 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2884 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
2893 rtl_set_def_aspm_entry_latency(tp);
2895 rtl_ephy_init(tp, e_info_8168e_2);
2897 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2898 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2899 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2900 rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2901 rtl_eri_set_bits(tp, 0x1d0, BIT(1));
2902 rtl_reset_packet_filter(tp);
2903 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2904 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2905 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060);
2907 rtl_disable_clock_request(tp);
2909 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2911 rtl8168_config_eee_mac(tp);
2913 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2914 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2915 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2917 rtl_hw_aspm_clkreq_enable(tp, true);
2920 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
2922 rtl_set_def_aspm_entry_latency(tp);
2924 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2925 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000);
2926 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06);
2927 rtl_reset_packet_filter(tp);
2928 rtl_eri_set_bits(tp, 0x1b0, BIT(4));
2929 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1));
2930 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050);
2931 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060);
2933 rtl_disable_clock_request(tp);
2935 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
2936 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
2937 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
2938 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
2940 rtl8168_config_eee_mac(tp);
2943 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
2954 rtl_hw_start_8168f(tp);
2956 rtl_ephy_init(tp, e_info_8168f_1);
2958 rtl_eri_set_bits(tp, 0x0d4, 0x1f00);
2961 static void rtl_hw_start_8411(struct rtl8169_private *tp)
2971 rtl_hw_start_8168f(tp);
2972 rtl_pcie_state_l2l3_disable(tp);
2974 rtl_ephy_init(tp, e_info_8168f_1);
2976 rtl_eri_set_bits(tp, 0x0d4, 0x0c00);
2979 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
2981 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
2982 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
2984 rtl_set_def_aspm_entry_latency(tp);
2986 rtl_reset_packet_filter(tp);
2987 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f);
2989 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
2991 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
2992 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
2993 rtl_eri_set_bits(tp, 0x0d4, 0x1f80);
2995 rtl8168_config_eee_mac(tp);
2997 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
2998 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3000 rtl_pcie_state_l2l3_disable(tp);
3003 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
3012 rtl_hw_start_8168g(tp);
3015 rtl_hw_aspm_clkreq_enable(tp, false);
3016 rtl_ephy_init(tp, e_info_8168g_1);
3017 rtl_hw_aspm_clkreq_enable(tp, true);
3020 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
3034 rtl_hw_start_8168g(tp);
3037 rtl_hw_aspm_clkreq_enable(tp, false);
3038 rtl_ephy_init(tp, e_info_8168g_2);
3041 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
3056 rtl_hw_start_8168g(tp);
3059 rtl_hw_aspm_clkreq_enable(tp, false);
3060 rtl_ephy_init(tp, e_info_8411_2);
3065 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
3066 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
3067 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
3068 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
3069 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
3070 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
3071 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
3072 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
3074 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
3076 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
3077 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
3078 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
3079 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
3080 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
3081 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
3082 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
3083 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
3084 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
3085 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
3086 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
3087 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
3088 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
3089 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
3090 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
3091 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
3092 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
3093 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
3094 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
3095 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
3096 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
3097 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
3098 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
3099 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
3100 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
3101 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
3102 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
3103 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
3104 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
3105 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
3106 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
3107 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
3108 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
3109 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
3110 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
3111 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
3112 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
3113 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
3114 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
3115 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
3116 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
3117 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
3118 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
3119 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
3120 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
3121 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
3122 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
3123 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
3124 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
3125 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
3126 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
3127 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
3128 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
3129 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
3130 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
3131 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
3132 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
3133 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
3134 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
3135 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
3136 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
3137 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
3138 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
3139 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
3140 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
3141 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
3142 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
3143 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
3144 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
3145 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
3146 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
3147 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
3148 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
3149 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
3150 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
3151 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
3152 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
3153 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
3154 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
3155 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
3156 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
3157 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
3158 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
3159 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
3160 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
3161 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
3162 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
3163 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
3164 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
3165 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
3166 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
3167 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
3168 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
3169 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
3170 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
3171 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
3172 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
3173 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
3174 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
3175 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
3176 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
3177 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
3178 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
3179 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
3180 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
3181 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
3182 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
3183 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
3184 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
3185 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
3186 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
3188 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
3190 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
3191 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
3192 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
3193 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
3194 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
3195 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
3196 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
3198 rtl_hw_aspm_clkreq_enable(tp, true);
3201 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
3214 rtl_hw_aspm_clkreq_enable(tp, false);
3215 rtl_ephy_init(tp, e_info_8168h_1);
3217 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3218 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48);
3220 rtl_set_def_aspm_entry_latency(tp);
3222 rtl_reset_packet_filter(tp);
3224 rtl_eri_set_bits(tp, 0xd4, 0x1f00);
3225 rtl_eri_set_bits(tp, 0xdc, 0x001c);
3227 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3229 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3231 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3232 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3234 rtl8168_config_eee_mac(tp);
3236 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3237 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3239 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3241 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3243 rtl_pcie_state_l2l3_disable(tp);
3245 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3251 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3254 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3255 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008);
3256 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f);
3257 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3259 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3260 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3261 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3262 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3264 rtl_hw_aspm_clkreq_enable(tp, true);
3267 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
3269 rtl8168ep_stop_cmac(tp);
3271 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3272 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3274 rtl_set_def_aspm_entry_latency(tp);
3276 rtl_reset_packet_filter(tp);
3278 rtl_eri_set_bits(tp, 0xd4, 0x1f80);
3280 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3282 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3284 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3285 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3287 rtl8168_config_eee_mac(tp);
3289 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06);
3291 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3293 rtl_pcie_state_l2l3_disable(tp);
3296 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
3307 rtl_hw_aspm_clkreq_enable(tp, false);
3308 rtl_ephy_init(tp, e_info_8168ep_1);
3310 rtl_hw_start_8168ep(tp);
3312 rtl_hw_aspm_clkreq_enable(tp, true);
3315 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
3324 rtl_hw_aspm_clkreq_enable(tp, false);
3325 rtl_ephy_init(tp, e_info_8168ep_2);
3327 rtl_hw_start_8168ep(tp);
3329 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3330 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3332 rtl_hw_aspm_clkreq_enable(tp, true);
3335 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
3345 rtl_hw_aspm_clkreq_enable(tp, false);
3346 rtl_ephy_init(tp, e_info_8168ep_3);
3348 rtl_hw_start_8168ep(tp);
3350 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3351 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3353 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271);
3354 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3355 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3357 rtl_hw_aspm_clkreq_enable(tp, true);
3360 static void rtl_hw_start_8117(struct rtl8169_private *tp)
3368 rtl8168ep_stop_cmac(tp);
3371 rtl_hw_aspm_clkreq_enable(tp, false);
3372 rtl_ephy_init(tp, e_info_8117);
3374 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06);
3375 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f);
3377 rtl_set_def_aspm_entry_latency(tp);
3379 rtl_reset_packet_filter(tp);
3381 rtl_eri_set_bits(tp, 0xd4, 0x1f90);
3383 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87);
3385 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3387 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3388 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3390 rtl8168_config_eee_mac(tp);
3392 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3393 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
3395 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
3397 rtl_eri_clear_bits(tp, 0x1b0, BIT(12));
3399 rtl_pcie_state_l2l3_disable(tp);
3401 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff;
3406 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini);
3409 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070);
3410 r8168_mac_ocp_write(tp, 0xea80, 0x0003);
3411 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009);
3412 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f);
3414 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
3415 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
3416 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
3417 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
3420 r8169_apply_firmware(tp);
3422 rtl_hw_aspm_clkreq_enable(tp, true);
3425 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
3439 rtl_set_def_aspm_entry_latency(tp);
3441 RTL_W8(tp, DBG_REG, FIX_NAK_1);
3443 RTL_W8(tp, Config1,
3445 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3447 cfg1 = RTL_R8(tp, Config1);
3449 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
3451 rtl_ephy_init(tp, e_info_8102e_1);
3454 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
3456 rtl_set_def_aspm_entry_latency(tp);
3458 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
3459 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3462 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
3464 rtl_hw_start_8102e_2(tp);
3466 rtl_ephy_write(tp, 0x03, 0xc2f9);
3469 static void rtl_hw_start_8401(struct rtl8169_private *tp)
3478 rtl_ephy_init(tp, e_info_8401);
3479 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
3482 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
3496 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3499 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
3501 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3502 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
3504 rtl_ephy_init(tp, e_info_8105e_1);
3506 rtl_pcie_state_l2l3_disable(tp);
3509 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
3511 rtl_hw_start_8105e_1(tp);
3512 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
3515 static void rtl_hw_start_8402(struct rtl8169_private *tp)
3522 rtl_set_def_aspm_entry_latency(tp);
3525 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3527 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
3529 rtl_ephy_init(tp, e_info_8402);
3531 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06);
3532 rtl_reset_packet_filter(tp);
3533 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000);
3534 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000);
3535 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00);
3538 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3540 rtl_pcie_state_l2l3_disable(tp);
3543 static void rtl_hw_start_8106(struct rtl8169_private *tp)
3545 rtl_hw_aspm_clkreq_enable(tp, false);
3548 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
3550 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
3551 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
3552 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
3554 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000);
3557 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000);
3559 rtl_pcie_state_l2l3_disable(tp);
3560 rtl_hw_aspm_clkreq_enable(tp, true);
3565 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13);
3568 static void rtl_hw_start_8125_common(struct rtl8169_private *tp)
3570 rtl_pcie_state_l2l3_disable(tp);
3572 RTL_W16(tp, 0x382, 0x221b);
3573 RTL_W8(tp, 0x4500, 0);
3574 RTL_W16(tp, 0x4800, 0);
3577 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000);
3579 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10);
3581 r8168_mac_ocp_write(tp, 0xc140, 0xffff);
3582 r8168_mac_ocp_write(tp, 0xc142, 0xffff);
3584 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9);
3585 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000);
3586 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080);
3589 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000);
3591 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3592 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200);
3594 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400);
3596 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3597 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000);
3599 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020);
3601 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c);
3602 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033);
3603 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040);
3604 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030);
3605 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000);
3606 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001);
3607 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403);
3608 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068);
3609 r8168_mac_ocp_modify(tp, 0xc0ac, 0x0080, 0x1f00);
3610 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f);
3612 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000);
3613 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001);
3615 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000);
3616 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030);
3618 r8168_mac_ocp_write(tp, 0xe098, 0xc302);
3620 rtl_loop_wait_low(tp, &rtl_mac_ocp_e00e_cond, 1000, 10);
3622 if (tp->mac_version == RTL_GIGA_MAC_VER_63)
3623 rtl8125b_config_eee_mac(tp);
3625 rtl8125a_config_eee_mac(tp);
3627 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
3631 static void rtl_hw_start_8125a_1(struct rtl8169_private *tp)
3661 rtl_set_def_aspm_entry_latency(tp);
3664 rtl_hw_aspm_clkreq_enable(tp, false);
3665 rtl_ephy_init(tp, e_info_8125a_1);
3667 rtl_hw_start_8125_common(tp);
3668 rtl_hw_aspm_clkreq_enable(tp, true);
3671 static void rtl_hw_start_8125a_2(struct rtl8169_private *tp)
3689 rtl_set_def_aspm_entry_latency(tp);
3692 rtl_hw_aspm_clkreq_enable(tp, false);
3693 rtl_ephy_init(tp, e_info_8125a_2);
3695 rtl_hw_start_8125_common(tp);
3696 rtl_hw_aspm_clkreq_enable(tp, true);
3699 static void rtl_hw_start_8125b(struct rtl8169_private *tp)
3710 rtl_set_def_aspm_entry_latency(tp);
3711 rtl_hw_aspm_clkreq_enable(tp, false);
3713 rtl_ephy_init(tp, e_info_8125b);
3714 rtl_hw_start_8125_common(tp);
3716 rtl_hw_aspm_clkreq_enable(tp, true);
3719 static void rtl_hw_config(struct rtl8169_private *tp)
3772 if (hw_configs[tp->mac_version])
3773 hw_configs[tp->mac_version](tp);
3776 static void rtl_hw_start_8125(struct rtl8169_private *tp)
3782 RTL_W32(tp, i, 0);
3784 rtl_hw_config(tp);
3787 static void rtl_hw_start_8168(struct rtl8169_private *tp)
3789 if (rtl_is_8168evl_up(tp))
3790 RTL_W8(tp, MaxTxPacketSize, EarlySize);
3792 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
3794 rtl_hw_config(tp);
3797 RTL_W16(tp, IntrMitigate, 0x0000);
3800 static void rtl_hw_start_8169(struct rtl8169_private *tp)
3802 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
3804 tp->cp_cmd |= PCIMulRW;
3806 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3807 tp->mac_version == RTL_GIGA_MAC_VER_03)
3808 tp->cp_cmd |= EnAnaPLL;
3810 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3812 rtl8169_set_magic_reg(tp);
3815 RTL_W16(tp, IntrMitigate, 0x0000);
3818 static void rtl_hw_start(struct rtl8169_private *tp)
3820 rtl_unlock_config_regs(tp);
3822 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
3824 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
3825 rtl_hw_start_8169(tp);
3826 else if (rtl_is_8125(tp))
3827 rtl_hw_start_8125(tp);
3829 rtl_hw_start_8168(tp);
3831 rtl_set_rx_max_size(tp);
3832 rtl_set_rx_tx_desc_registers(tp);
3833 rtl_lock_config_regs(tp);
3835 rtl_jumbo_config(tp);
3838 rtl_pci_commit(tp);
3840 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
3841 rtl_init_rxcfg(tp);
3842 rtl_set_tx_config_registers(tp);
3843 rtl_set_rx_config_features(tp, tp->dev->features);
3844 rtl_set_rx_mode(tp->dev);
3845 rtl_irq_enable(tp);
3850 struct rtl8169_private *tp = netdev_priv(dev);
3854 rtl_jumbo_config(tp);
3856 switch (tp->mac_version) {
3859 rtl8125_set_eee_txidle_timer(tp);
3878 static struct page *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
3881 struct device *d = tp_to_dev(tp);
3892 netdev_err(tp->dev, "Failed to map RX DMA!\n");
3903 static void rtl8169_rx_clear(struct rtl8169_private *tp)
3907 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) {
3908 dma_unmap_page(tp_to_dev(tp),
3909 le64_to_cpu(tp->RxDescArray[i].addr),
3911 __free_pages(tp->Rx_databuff[i], get_order(R8169_RX_BUF_SIZE));
3912 tp->Rx_databuff[i] = NULL;
3913 tp->RxDescArray[i].addr = 0;
3914 tp->RxDescArray[i].opts1 = 0;
3918 static int rtl8169_rx_fill(struct rtl8169_private *tp)
3925 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
3927 rtl8169_rx_clear(tp);
3930 tp->Rx_databuff[i] = data;
3934 tp->RxDescArray[NUM_RX_DESC - 1].opts1 |= cpu_to_le32(RingEnd);
3939 static int rtl8169_init_ring(struct rtl8169_private *tp)
3941 rtl8169_init_ring_indexes(tp);
3943 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
3944 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
3946 return rtl8169_rx_fill(tp);
3949 static void rtl8169_unmap_tx_skb(struct rtl8169_private *tp, unsigned int entry)
3951 struct ring_info *tx_skb = tp->tx_skb + entry;
3952 struct TxDesc *desc = tp->TxDescArray + entry;
3954 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr), tx_skb->len,
3960 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
3967 struct ring_info *tx_skb = tp->tx_skb + entry;
3973 rtl8169_unmap_tx_skb(tp, entry);
3980 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3982 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
3983 netdev_reset_queue(tp->dev);
3986 static void rtl8169_cleanup(struct rtl8169_private *tp, bool going_down)
3988 napi_disable(&tp->napi);
3994 rtl8169_irq_mask_and_ack(tp);
3996 rtl_rx_close(tp);
3998 if (going_down && tp->dev->wol_enabled)
4001 switch (tp->mac_version) {
4005 rtl_loop_wait_low(tp, &rtl_npq_cond, 20, 2000);
4008 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4009 rtl_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4012 rtl_enable_rxdvgate(tp);
4016 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4021 rtl_hw_reset(tp);
4023 rtl8169_tx_clear(tp);
4024 rtl8169_init_ring_indexes(tp);
4027 static void rtl_reset_work(struct rtl8169_private *tp)
4031 netif_stop_queue(tp->dev);
4033 rtl8169_cleanup(tp, false);
4036 rtl8169_mark_to_asic(tp->RxDescArray + i);
4038 napi_enable(&tp->napi);
4039 rtl_hw_start(tp);
4044 struct rtl8169_private *tp = netdev_priv(dev);
4046 rtl_schedule_task(tp, RTL_FLAG_TASK_TX_TIMEOUT);
4049 static int rtl8169_tx_map(struct rtl8169_private *tp, const u32 *opts, u32 len,
4052 struct TxDesc *txd = tp->TxDescArray + entry;
4053 struct device *d = tp_to_dev(tp);
4062 netdev_err(tp->dev, "Failed to map TX data!\n");
4076 tp->tx_skb[entry].len = len;
4081 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4094 if (unlikely(rtl8169_tx_map(tp, opts, len, addr, entry, true)))
4101 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4126 static unsigned int rtl8125_quirk_udp_padto(struct rtl8169_private *tp,
4131 if (rtl_is_8125(tp) && len < 128 + RTL_MIN_PATCH_LEN &&
4153 static unsigned int rtl_quirk_packet_padto(struct rtl8169_private *tp,
4158 padto = rtl8125_quirk_udp_padto(tp, skb);
4160 switch (tp->mac_version) {
4192 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
4241 unsigned int padto = rtl_quirk_packet_padto(tp, skb);
4250 static bool rtl_tx_slots_avail(struct rtl8169_private *tp,
4253 unsigned int slots_avail = tp->dirty_tx + NUM_TX_DESC - tp->cur_tx;
4260 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
4262 switch (tp->mac_version) {
4271 static void rtl8169_doorbell(struct rtl8169_private *tp)
4273 if (rtl_is_8125(tp))
4274 RTL_W16(tp, TxPoll_8125, BIT(0));
4276 RTL_W8(tp, TxPoll, NPQ);
4283 struct rtl8169_private *tp = netdev_priv(dev);
4284 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4289 txd_first = tp->TxDescArray + entry;
4291 if (unlikely(!rtl_tx_slots_avail(tp, frags))) {
4303 if (!rtl_chip_supports_csum_v2(tp))
4305 else if (!rtl8169_tso_csum_v2(tp, skb, opts))
4308 if (unlikely(rtl8169_tx_map(tp, opts, skb_headlen(skb), skb->data,
4313 if (rtl8169_xmit_frags(tp, skb, opts, entry))
4318 txd_last = tp->TxDescArray + entry;
4320 tp->tx_skb[entry].skb = skb;
4331 /* rtl_tx needs to see descriptor changes before updated tp->cur_tx */
4334 tp->cur_tx += frags + 1;
4336 stop_queue = !rtl_tx_slots_avail(tp, MAX_SKB_FRAGS);
4347 rtl8169_doorbell(tp);
4358 if (rtl_tx_slots_avail(tp, MAX_SKB_FRAGS))
4365 rtl8169_unmap_tx_skb(tp, entry);
4412 struct rtl8169_private *tp = netdev_priv(dev);
4415 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4419 rtl_chip_supports_csum_v2(tp))
4426 if (rtl_quirk_packet_padto(tp, skb))
4430 rtl_chip_supports_csum_v2(tp))
4439 struct rtl8169_private *tp = netdev_priv(dev);
4440 struct pci_dev *pdev = tp->pci_dev;
4466 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4469 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp,
4474 dirty_tx = tp->dirty_tx;
4477 for (tx_left = tp->cur_tx - dirty_tx; tx_left > 0; tx_left--) {
4479 struct sk_buff *skb = tp->tx_skb[entry].skb;
4482 status = le32_to_cpu(READ_ONCE(tp->TxDescArray[entry].opts1));
4486 rtl8169_unmap_tx_skb(tp, entry);
4496 if (tp->dirty_tx != dirty_tx) {
4499 rtl_inc_priv_stats(&tp->tx_stats, pkts_compl, bytes_compl);
4501 tp->dirty_tx = dirty_tx;
4511 rtl_tx_slots_avail(tp, MAX_SKB_FRAGS)) {
4520 if (tp->cur_tx != dirty_tx)
4521 rtl8169_doorbell(tp);
4541 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
4544 struct device *d = tp_to_dev(tp);
4546 cur_rx = tp->cur_rx;
4550 struct RxDesc *desc = tp->RxDescArray + entry;
4595 skb = napi_alloc_skb(&tp->napi, pkt_size);
4602 rx_buf = page_address(tp->Rx_databuff[entry]);
4619 napi_gro_receive(&tp->napi, skb);
4621 rtl_inc_priv_stats(&tp->rx_stats, 1, pkt_size);
4626 count = cur_rx - tp->cur_rx;
4627 tp->cur_rx = cur_rx;
4634 struct rtl8169_private *tp = dev_instance;
4635 u32 status = rtl_get_events(tp);
4637 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask))
4641 rtl8169_pcierr_interrupt(tp->dev);
4646 phy_mac_interrupt(tp->phydev);
4649 tp->mac_version == RTL_GIGA_MAC_VER_11)) {
4650 netif_stop_queue(tp->dev);
4651 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
4654 rtl_irq_disable(tp);
4655 napi_schedule(&tp->napi);
4657 rtl_ack_events(tp, status);
4664 struct rtl8169_private *tp =
4670 if (!netif_running(tp->dev) ||
4671 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
4674 if (test_and_clear_bit(RTL_FLAG_TASK_TX_TIMEOUT, tp->wk.flags)) {
4676 ret = pci_disable_link_state(tp->pci_dev, PCIE_LINK_STATE_L1 |
4679 netdev_warn_once(tp->dev, "ASPM disabled on Tx timeout\n");
4683 if (test_and_clear_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags)) {
4685 rtl_reset_work(tp);
4686 netif_wake_queue(tp->dev);
4687 } else if (test_and_clear_bit(RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE, tp->wk.flags)) {
4688 rtl_reset_work(tp);
4696 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
4697 struct net_device *dev = tp->dev;
4700 work_done = rtl_rx(dev, tp, (u32) budget);
4702 rtl_tx(dev, tp, budget);
4705 rtl_irq_enable(tp);
4712 struct rtl8169_private *tp = netdev_priv(ndev);
4713 struct device *d = tp_to_dev(tp);
4716 rtl_link_chg_patch(tp);
4718 netif_wake_queue(tp->dev);
4721 if (rtl_is_8125(tp))
4722 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_NO_QUEUE_WAKE);
4727 phy_print_status(tp->phydev);
4730 static int r8169_phy_connect(struct rtl8169_private *tp)
4732 struct phy_device *phydev = tp->phydev;
4736 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
4739 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
4744 if (!tp->supports_gmii)
4752 static void rtl8169_down(struct rtl8169_private *tp)
4755 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
4757 phy_stop(tp->phydev);
4759 rtl8169_update_counters(tp);
4761 pci_clear_master(tp->pci_dev);
4762 rtl_pci_commit(tp);
4764 rtl8169_cleanup(tp, true);
4766 rtl_pll_power_down(tp);
4769 static void rtl8169_up(struct rtl8169_private *tp)
4771 pci_set_master(tp->pci_dev);
4772 rtl_pll_power_up(tp);
4773 rtl8169_init_phy(tp);
4774 napi_enable(&tp->napi);
4775 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
4776 rtl_reset_work(tp);
4778 phy_start(tp->phydev);
4783 struct rtl8169_private *tp = netdev_priv(dev);
4784 struct pci_dev *pdev = tp->pci_dev;
4789 rtl8169_down(tp);
4790 rtl8169_rx_clear(tp);
4792 cancel_work(&tp->wk.work);
4794 free_irq(pci_irq_vector(pdev, 0), tp);
4796 phy_disconnect(tp->phydev);
4798 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4799 tp->RxPhyAddr);
4800 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4801 tp->TxPhyAddr);
4802 tp->TxDescArray = NULL;
4803 tp->RxDescArray = NULL;
4813 struct rtl8169_private *tp = netdev_priv(dev);
4815 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
4821 struct rtl8169_private *tp = netdev_priv(dev);
4822 struct pci_dev *pdev = tp->pci_dev;
4831 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
4832 &tp->TxPhyAddr, GFP_KERNEL);
4833 if (!tp->TxDescArray)
4836 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
4837 &tp->RxPhyAddr, GFP_KERNEL);
4838 if (!tp->RxDescArray)
4841 retval = rtl8169_init_ring(tp);
4845 rtl_request_firmware(tp);
4848 IRQF_SHARED, dev->name, tp);
4852 retval = r8169_phy_connect(tp);
4856 rtl8169_up(tp);
4857 rtl8169_init_counter_offsets(tp);
4865 free_irq(pci_irq_vector(pdev, 0), tp);
4867 rtl_release_firmware(tp);
4868 rtl8169_rx_clear(tp);
4870 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
4871 tp->RxPhyAddr);
4872 tp->RxDescArray = NULL;
4874 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
4875 tp->TxPhyAddr);
4876 tp->TxDescArray = NULL;
4885 struct rtl8169_private *tp = netdev_priv(dev);
4886 struct pci_dev *pdev = tp->pci_dev;
4887 struct rtl8169_counters *counters = tp->counters;
4893 rtl_get_priv_stats(&tp->rx_stats, &stats->rx_packets, &stats->rx_bytes);
4894 rtl_get_priv_stats(&tp->tx_stats, &stats->tx_packets, &stats->tx_bytes);
4901 rtl8169_update_counters(tp);
4908 le64_to_cpu(tp->tc_offset.tx_errors);
4910 le32_to_cpu(tp->tc_offset.tx_multi_collision);
4912 le16_to_cpu(tp->tc_offset.tx_aborted);
4914 le16_to_cpu(tp->tc_offset.rx_missed);
4919 static void rtl8169_net_suspend(struct rtl8169_private *tp)
4921 netif_device_detach(tp->dev);
4923 if (netif_running(tp->dev))
4924 rtl8169_down(tp);
4929 static int rtl8169_net_resume(struct rtl8169_private *tp)
4931 rtl_rar_set(tp, tp->dev->dev_addr);
4933 if (tp->TxDescArray)
4934 rtl8169_up(tp);
4936 netif_device_attach(tp->dev);
4943 struct rtl8169_private *tp = dev_get_drvdata(device);
4946 rtl8169_net_suspend(tp);
4947 if (!device_may_wakeup(tp_to_dev(tp)))
4948 clk_disable_unprepare(tp->clk);
4956 struct rtl8169_private *tp = dev_get_drvdata(device);
4958 if (!device_may_wakeup(tp_to_dev(tp)))
4959 clk_prepare_enable(tp->clk);
4962 if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4963 rtl_init_rxcfg(tp);
4965 return rtl8169_net_resume(tp);
4970 struct rtl8169_private *tp = dev_get_drvdata(device);
4972 if (!tp->TxDescArray) {
4973 netif_device_detach(tp->dev);
4978 __rtl8169_set_wol(tp, WAKE_PHY);
4979 rtl8169_net_suspend(tp);
4987 struct rtl8169_private *tp = dev_get_drvdata(device);
4989 __rtl8169_set_wol(tp, tp->saved_wolopts);
4991 return rtl8169_net_resume(tp);
4996 struct rtl8169_private *tp = dev_get_drvdata(device);
4998 if (!netif_running(tp->dev) || !netif_carrier_ok(tp->dev))
5012 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
5015 switch (tp->mac_version) {
5019 pci_clear_master(tp->pci_dev);
5021 RTL_W8(tp, ChipCmd, CmdRxEnb);
5022 rtl_pci_commit(tp);
5031 struct rtl8169_private *tp = pci_get_drvdata(pdev);
5034 rtl8169_net_suspend(tp);
5038 rtl_rar_set(tp, tp->dev->perm_addr);
5041 if (tp->saved_wolopts) {
5042 rtl_wol_suspend_quirk(tp);
5043 rtl_wol_shutdown_quirk(tp);
5053 struct rtl8169_private *tp = pci_get_drvdata(pdev);
5058 cancel_work_sync(&tp->wk.work);
5060 unregister_netdev(tp->dev);
5062 if (r8168_check_dash(tp))
5063 rtl8168_driver_stop(tp);
5065 rtl_release_firmware(tp);
5068 rtl_rar_set(tp, tp->dev->perm_addr);
5091 static void rtl_set_irq_mask(struct rtl8169_private *tp)
5093 tp->irq_mask = RxOK | RxErr | TxOK | TxErr | LinkChg;
5095 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
5096 tp->irq_mask |= SYSErr | RxOverflow | RxFIFOOver;
5097 else if (tp->mac_version == RTL_GIGA_MAC_VER_11)
5099 tp->irq_mask |= RxFIFOOver;
5101 tp->irq_mask |= RxOverflow;
5104 static int rtl_alloc_irq(struct rtl8169_private *tp)
5108 switch (tp->mac_version) {
5110 rtl_unlock_config_regs(tp);
5111 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
5112 rtl_lock_config_regs(tp);
5122 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
5125 static void rtl_read_mac_address(struct rtl8169_private *tp,
5129 if (rtl_is_8168evl_up(tp) && tp->mac_version != RTL_GIGA_MAC_VER_34) {
5130 u32 value = rtl_eri_read(tp, 0xe0);
5137 value = rtl_eri_read(tp, 0xe4);
5140 } else if (rtl_is_8125(tp)) {
5141 rtl_read_mac_from_reg(tp, mac_addr, MAC0_BKP);
5147 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
5150 static void r8168g_wait_ll_share_fifo_ready(struct rtl8169_private *tp)
5152 rtl_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42);
5157 struct rtl8169_private *tp = mii_bus->priv;
5162 return rtl_readphy(tp, phyreg);
5168 struct rtl8169_private *tp = mii_bus->priv;
5173 rtl_writephy(tp, phyreg, val);
5178 static int r8169_mdio_register(struct rtl8169_private *tp)
5180 struct pci_dev *pdev = tp->pci_dev;
5189 new_bus->priv = tp;
5202 tp->phydev = mdiobus_get_phy(new_bus, 0);
5203 if (!tp->phydev) {
5205 } else if (!tp->phydev->drv) {
5210 tp->phydev->phy_id);
5215 phy_suspend(tp->phydev);
5220 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
5222 rtl_enable_rxdvgate(tp);
5224 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5226 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5228 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5229 r8168g_wait_ll_share_fifo_ready(tp);
5231 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15));
5232 r8168g_wait_ll_share_fifo_ready(tp);
5235 static void rtl_hw_init_8125(struct rtl8169_private *tp)
5237 rtl_enable_rxdvgate(tp);
5239 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
5241 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5243 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0);
5244 r8168g_wait_ll_share_fifo_ready(tp);
5246 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0);
5247 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150);
5248 r8168_mac_ocp_write(tp, 0xc01e, 0x5555);
5249 r8168g_wait_ll_share_fifo_ready(tp);
5252 static void rtl_hw_initialize(struct rtl8169_private *tp)
5254 switch (tp->mac_version) {
5256 rtl8168ep_stop_cmac(tp);
5259 rtl_hw_init_8168g(tp);
5262 rtl_hw_init_8125(tp);
5269 static int rtl_jumbo_max(struct rtl8169_private *tp)
5272 if (!tp->supports_gmii)
5275 switch (tp->mac_version) {
5297 static int rtl_get_ether_clk(struct rtl8169_private *tp)
5299 struct device *d = tp_to_dev(tp);
5312 tp->clk = clk;
5323 static void rtl_init_mac_address(struct rtl8169_private *tp)
5325 struct net_device *dev = tp->dev;
5329 rc = eth_platform_get_mac_address(tp_to_dev(tp), mac_addr);
5333 rtl_read_mac_address(tp, mac_addr);
5337 rtl_read_mac_from_reg(tp, mac_addr, MAC0);
5342 dev_warn(tp_to_dev(tp), "can't read MAC address, setting random one\n");
5344 rtl_rar_set(tp, mac_addr);
5349 struct rtl8169_private *tp;
5355 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
5361 tp = netdev_priv(dev);
5362 tp->dev = dev;
5363 tp->pci_dev = pdev;
5364 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1;
5365 tp->eee_adv = -1;
5366 tp->ocp_base = OCP_STD_PHY_BASE;
5369 rc = rtl_get_ether_clk(tp);
5378 tp->aspm_manageable = !rc;
5409 tp->mmio_addr = pcim_iomap_table(pdev)[region];
5411 xid = (RTL_R32(tp, TxConfig) >> 20) & 0xfcf;
5414 chipset = rtl8169_get_mac_version(xid, tp->supports_gmii);
5420 tp->mac_version = chipset;
5422 tp->cp_cmd = RTL_R16(tp, CPlusCmd) & CPCMD_MASK;
5424 if (sizeof(dma_addr_t) > 4 && tp->mac_version >= RTL_GIGA_MAC_VER_18 &&
5428 rtl_init_rxcfg(tp);
5430 rtl8169_irq_mask_and_ack(tp);
5432 rtl_hw_initialize(tp);
5434 rtl_hw_reset(tp);
5436 rc = rtl_alloc_irq(tp);
5442 INIT_WORK(&tp->wk.work, rtl_task);
5443 u64_stats_init(&tp->rx_stats.syncp);
5444 u64_stats_init(&tp->tx_stats.syncp);
5446 rtl_init_mac_address(tp);
5450 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
5461 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
5465 if (rtl_chip_supports_csum_v2(tp))
5475 if (rtl_chip_supports_csum_v2(tp)) {
5491 jumbo_max = rtl_jumbo_max(tp);
5495 rtl_set_irq_mask(tp);
5497 tp->fw_name = rtl_chip_infos[chipset].fw_name;
5499 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
5500 &tp->counters_phys_addr,
5502 if (!tp->counters)
5505 pci_set_drvdata(pdev, tp);
5507 rc = r8169_mdio_register(tp);
5512 rtl_pll_power_down(tp);
5524 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
5527 if (r8168_check_dash(tp)) {
5529 rtl8168_driver_start(tp);