Lines Matching refs:value
108 u32 value;
114 value = readl(&port_regs->CommonRegs.semaphoreReg);
115 if ((value & (sem_mask >> 16)) == sem_bits)
134 u32 value;
137 value = readl(&port_regs->CommonRegs.semaphoreReg);
138 return ((value & (sem_mask >> 16)) == sem_bits);
177 u32 value;
181 value = readl(reg);
184 return value;
194 u32 value;
201 value = readl(reg);
204 return value;
215 u32 __iomem *reg, u32 value)
220 writel(value, reg);
226 u32 __iomem *reg, u32 value)
228 writel(value, reg);
233 u32 __iomem *reg, u32 value)
235 writel(value, reg);
241 u32 __iomem *reg, u32 value)
245 writel(value, reg);
253 u32 __iomem *reg, u32 value)
257 writel(value, reg);
265 u32 __iomem *reg, u32 value)
269 writel(value, reg);
368 unsigned short *value);
472 static void fm93c56a_datain(struct ql3_adapter *qdev, unsigned short *value)
494 *value = (u16)data;
501 u32 eepromAddr, unsigned short *value)
505 fm93c56a_datain(qdev, value);
633 u16 regAddr, u16 value, u32 phyAddr)
649 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
664 u16 *value, u32 phyAddr)
694 *value = (u16) temp;
702 static int ql_mii_write_reg(struct ql3_adapter *qdev, u16 regAddr, u16 value)
717 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
730 static int ql_mii_read_reg(struct ql3_adapter *qdev, u16 regAddr, u16 *value)
759 *value = (u16) temp;
1036 u32 value;
1039 value = (MAC_CONFIG_REG_PE | (MAC_CONFIG_REG_PE << 16));
1041 value = (MAC_CONFIG_REG_PE << 16);
1044 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1046 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1056 u32 value;
1059 value = (MAC_CONFIG_REG_SR | (MAC_CONFIG_REG_SR << 16));
1061 value = (MAC_CONFIG_REG_SR << 16);
1064 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1066 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1076 u32 value;
1079 value = (MAC_CONFIG_REG_GM | (MAC_CONFIG_REG_GM << 16));
1081 value = (MAC_CONFIG_REG_GM << 16);
1084 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1086 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1096 u32 value;
1099 value = (MAC_CONFIG_REG_FD | (MAC_CONFIG_REG_FD << 16));
1101 value = (MAC_CONFIG_REG_FD << 16);
1104 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1106 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1116 u32 value;
1119 value =
1123 value = ((MAC_CONFIG_REG_TF | MAC_CONFIG_REG_RF) << 16);
1126 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1128 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1344 be reinterpreted with a default value */
1750 static void ql_set_msglevel(struct net_device *ndev, u32 value)
1753 qdev->msg_enable = value;
2204 u32 value;
2208 value = ql_read_common_reg_l(qdev,
2211 if (value & (ISP_CONTROL_FE | ISP_CONTROL_RI)) {
2219 if (value & ISP_CONTROL_FE) {
2236 "Another function issued a reset to the chip. ISR value = %x\n",
2237 value);
2241 } else if (value & ISP_IMR_DISABLE_CMPL_INT) {
2995 u32 value;
3120 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3121 if ((value & PORT_STATUS_IC) == 0) {
3129 value = qdev->nvram_data.tcpMaxWindowSize;
3130 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3132 value = (0xFFFF << 16) | qdev->nvram_data.extHwConfig;
3140 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3210 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3211 if (value & PORT_STATUS_IC)
3226 value =
3231 ((value << 16) | value));
3233 value =
3237 ((value << 16) | value));
3253 u16 value;
3274 value =
3277 if ((value & ISP_CONTROL_SR) == 0)
3287 value =
3289 if (value & ISP_CONTROL_RI) {
3311 value = ql_read_common_reg(qdev,
3314 if ((value & ISP_CONTROL_FSR) == 0)
3331 u32 value, port_status;
3335 value =
3337 func_number = (u8) ((value >> 4) & OPCODE_FUNC_ID_MASK);
3339 switch (value & ISP_CONTROL_FN_MASK) {
3367 value);
3611 u32 value;
3657 value = ql_read_common_reg(qdev,
3661 if ((value & ISP_CONTROL_SR) == 0) {
3667 if (value & ISP_CONTROL_RI) {
3684 if (value & ISP_CONTROL_SR) {
3718 u32 value;
3720 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);
3722 qdev->chip_rev_id = ((value & PORT_STATUS_REV_ID_MASK) >> 12);
3723 if (value & PORT_STATUS_64)
3727 if (value & PORT_STATUS_X)
3851 * Set the Maximum Memory Read Byte Count value. We do this to handle