Lines Matching defs:port_regs
106 struct ql3xxx_port_registers __iomem *port_regs =
113 &port_regs->CommonRegs.semaphoreReg);
114 value = readl(&port_regs->CommonRegs.semaphoreReg);
124 struct ql3xxx_port_registers __iomem *port_regs =
126 writel(sem_mask, &port_regs->CommonRegs.semaphoreReg);
127 readl(&port_regs->CommonRegs.semaphoreReg);
132 struct ql3xxx_port_registers __iomem *port_regs =
136 writel((sem_mask | sem_bits), &port_regs->CommonRegs.semaphoreReg);
137 value = readl(&port_regs->CommonRegs.semaphoreReg);
166 struct ql3xxx_port_registers __iomem *port_regs =
170 &port_regs->CommonRegs.ispControlStatus);
171 readl(&port_regs->CommonRegs.ispControlStatus);
275 struct ql3xxx_port_registers __iomem *port_regs =
278 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
285 struct ql3xxx_port_registers __iomem *port_regs =
288 ql_write_common_reg_l(qdev, &port_regs->CommonRegs.ispInterruptMaskReg,
375 struct ql3xxx_port_registers __iomem *port_regs =
377 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
392 struct ql3xxx_port_registers __iomem *port_regs =
394 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
461 struct ql3xxx_port_registers __iomem *port_regs =
463 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
477 struct ql3xxx_port_registers __iomem *port_regs =
479 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
560 struct ql3xxx_port_registers __iomem *port_regs =
566 temp = ql_read_page0_reg(qdev, &port_regs->macMIIStatusReg);
577 struct ql3xxx_port_registers __iomem *port_regs =
594 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
597 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
605 struct ql3xxx_port_registers __iomem *port_regs =
609 if (ql_read_page0_reg(qdev, &port_regs->macMIIMgmtControlReg) &
622 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
625 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
635 struct ql3xxx_port_registers __iomem *port_regs =
646 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
649 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
666 struct ql3xxx_port_registers __iomem *port_regs =
678 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
681 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
684 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
693 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
704 struct ql3xxx_port_registers __iomem *port_regs =
714 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
717 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtDataReg, value);
733 struct ql3xxx_port_registers __iomem *port_regs =
743 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtAddrReg,
746 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
749 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
758 temp = ql_read_page0_reg(qdev, &port_regs->macMIIMgmtDataReg);
1034 struct ql3xxx_port_registers __iomem *port_regs =
1044 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1046 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1054 struct ql3xxx_port_registers __iomem *port_regs =
1064 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1066 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1074 struct ql3xxx_port_registers __iomem *port_regs =
1084 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1086 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1094 struct ql3xxx_port_registers __iomem *port_regs =
1104 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1106 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1114 struct ql3xxx_port_registers __iomem *port_regs =
1126 ql_write_page0_reg(qdev, &port_regs->mac1ConfigReg, value);
1128 ql_write_page0_reg(qdev, &port_regs->mac0ConfigReg, value);
1136 struct ql3xxx_port_registers __iomem *port_regs =
1150 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1166 struct ql3xxx_port_registers __iomem *port_regs =
1180 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1202 struct ql3xxx_port_registers __iomem *port_regs =
1215 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1240 struct ql3xxx_port_registers __iomem *port_regs =
1255 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
1264 struct ql3xxx_port_registers __iomem *port_regs =
1270 &port_regs->CommonRegs.ispControlStatus,
1277 &port_regs->CommonRegs.ispControlStatus,
1294 struct ql3xxx_port_registers __iomem *port_regs =
1310 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1412 struct ql3xxx_port_registers __iomem *port_regs =
1426 temp = ql_read_page0_reg(qdev, &port_regs->portStatus);
1613 struct ql3xxx_port_registers __iomem *port_regs =
1623 &port_regs->macMIIMgmtControlReg, 0x0f00000);
1628 ql_write_page0_reg(qdev, &port_regs->macMIIMgmtControlReg,
1760 struct ql3xxx_port_registers __iomem *port_regs =
1765 reg = ql_read_page0_reg(qdev, &port_regs->mac0ConfigReg);
1767 reg = ql_read_page0_reg(qdev, &port_regs->mac1ConfigReg);
1843 struct ql3xxx_port_registers __iomem *port_regs =
1857 &port_regs->CommonRegs.rxSmallQProducerIndex);
1869 struct ql3xxx_port_registers __iomem *port_regs =
1910 &port_regs->CommonRegs.rxLargeQProducerIndex);
2176 struct ql3xxx_port_registers __iomem *port_regs =
2189 &port_regs->CommonRegs.rspQConsumerIndex);
2202 struct ql3xxx_port_registers __iomem *port_regs =
2209 &port_regs->CommonRegs.ispControlStatus);
2225 &port_regs->PortFatalErrStatus);
2458 struct ql3xxx_port_registers __iomem *port_regs =
2499 &port_regs->CommonRegs.reqQProducerIndex,
2996 struct ql3xxx_port_registers __iomem *port_regs =
2998 __iomem u32 *spir = &port_regs->CommonRegs.serialPortInterfaceReg;
3000 (void __iomem *)port_regs;
3107 &port_regs->CommonRegs.
3111 &port_regs->CommonRegs.
3120 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3130 ql_write_page0_reg(qdev, &port_regs->tcpMaxWindow, value);
3140 ql_write_page0_reg(qdev, &port_regs->ExternalHWConfig, value);
3141 ql_write_page0_reg(qdev, &port_regs->InternalChipConfig,
3150 &port_regs->mac1MaxFrameLengthReg,
3154 &port_regs->mac0MaxFrameLengthReg,
3171 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3173 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3180 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3182 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3187 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3192 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3195 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3197 ql_write_page0_reg(qdev, &port_regs->ipAddrIndexReg,
3200 ql_write_page0_reg(qdev, &port_regs->ipAddrDataReg, 0);
3206 &port_regs->portControl,
3210 value = ql_read_page0_reg(qdev, &port_regs->portStatus);
3230 ql_write_page0_reg(qdev, &port_regs->functionControl,
3236 ql_write_page0_reg(qdev, &port_regs->portControl,
3250 struct ql3xxx_port_registers __iomem *port_regs =
3264 &port_regs->CommonRegs.ispControlStatus,
3276 &port_regs->CommonRegs.ispControlStatus);
3288 ql_read_common_reg(qdev, &port_regs->CommonRegs.ispControlStatus);
3293 &port_regs->CommonRegs.
3301 &port_regs->CommonRegs.
3312 &port_regs->CommonRegs.
3329 struct ql3xxx_port_registers __iomem *port_regs =
3336 ql_read_common_reg_l(qdev, &port_regs->CommonRegs.ispControlStatus);
3338 port_status = ql_read_page0_reg(qdev, &port_regs->portStatus);
3558 struct ql3xxx_port_registers __iomem *port_regs =
3573 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3575 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3581 ql_write_page0_reg(qdev, &port_regs->macAddrIndirectPtrReg,
3583 ql_write_page0_reg(qdev, &port_regs->macAddrDataReg,
3614 struct ql3xxx_port_registers __iomem *port_regs =
3649 &port_regs->CommonRegs.
3658 &port_regs->CommonRegs.
3671 &port_regs->
3716 struct ql3xxx_port_registers __iomem *port_regs =
3720 value = ql_read_page0_reg_l(qdev, &port_regs->portStatus);