Lines Matching refs:txreg
3312 u32 phyreg, txreg;
3347 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3349 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3351 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3353 writel(txreg, base + NvRegTxDeferral);
3356 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3360 txreg = NVREG_TX_WM_DESC2_3_1000;
3362 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3364 writel(txreg, base + NvRegTxWatermark);
3396 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3528 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3532 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3534 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3536 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3541 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3543 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3545 writel(txreg, base + NvRegTxDeferral);
3548 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3551 txreg = NVREG_TX_WM_DESC2_3_1000;
3553 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3555 writel(txreg, base + NvRegTxWatermark);
5715 u32 powerstate, txreg;
5893 txreg = readl(base + NvRegTransmitPoll);
5902 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5926 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);