Lines Matching refs:phyaddr
768 int phyaddr;
1186 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1195 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1220 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1242 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1244 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1246 if (mii_rw(dev, np->phyaddr,
1249 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1252 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1255 if (mii_rw(dev, np->phyaddr,
1267 phy_reserved = mii_rw(dev, np->phyaddr,
1270 if (mii_rw(dev, np->phyaddr,
1283 if (mii_rw(dev, np->phyaddr,
1286 phy_reserved = mii_rw(dev, np->phyaddr,
1290 if (mii_rw(dev, np->phyaddr,
1293 if (mii_rw(dev, np->phyaddr,
1307 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1310 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1312 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1314 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1317 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1319 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1329 if (mii_rw(dev, np->phyaddr,
1332 if (mii_rw(dev, np->phyaddr,
1335 phy_reserved = mii_rw(dev, np->phyaddr,
1337 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1339 phy_reserved = mii_rw(dev, np->phyaddr,
1343 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1345 if (mii_rw(dev, np->phyaddr,
1348 if (mii_rw(dev, np->phyaddr,
1351 phy_reserved = mii_rw(dev, np->phyaddr,
1355 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1357 phy_reserved = mii_rw(dev, np->phyaddr,
1359 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1361 if (mii_rw(dev, np->phyaddr,
1364 if (mii_rw(dev, np->phyaddr,
1367 phy_reserved = mii_rw(dev, np->phyaddr,
1369 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1371 phy_reserved = mii_rw(dev, np->phyaddr,
1375 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1377 if (mii_rw(dev, np->phyaddr,
1380 if (mii_rw(dev, np->phyaddr,
1396 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1398 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1429 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1433 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1443 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1446 mii_control_1000 = mii_rw(dev, np->phyaddr,
1454 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1462 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1470 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1519 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1522 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1526 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
3319 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3403 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3416 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3417 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3452 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3453 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3457 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3458 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3525 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
4383 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4393 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4405 cmd->base.phy_address = np->phyaddr;
4429 if (cmd->base.phy_address != np->phyaddr) {
4488 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4502 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4505 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4509 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4514 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4525 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4532 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4551 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4555 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4557 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4560 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4573 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4634 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4644 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4840 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4846 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4850 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4852 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4881 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4891 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol);
5035 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5036 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5465 mii_rw(dev, np->phyaddr, MII_BMCR,
5466 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5551 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5664 mii_rw(dev, np->phyaddr, MII_BMCR,
5665 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
6050 int phyaddr = i & 0x1F;
6053 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
6058 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
6066 np->phyaddr = phyaddr;
6074 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
6088 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
6118 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
6168 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
6169 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
6172 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
6173 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
6176 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
6178 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);