Lines Matching refs:base
752 /* in dev: base, irq */
794 void __iomem *base;
941 return ((struct fe_priv *)netdev_priv(dev))->base;
944 static inline void pci_push(u8 __iomem *base)
947 readl(base);
971 u8 __iomem *base = get_hwbase(dev);
973 pci_push(base);
979 } while ((readl(base + offset) & mask) != target);
999 u8 __iomem *base = get_hwbase(dev);
1003 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1005 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1008 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1009 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
1012 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1013 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
1056 u8 __iomem *base = get_hwbase(dev);
1061 powerstate = readl(base + NvRegPowerState2);
1066 writel(powerstate, base + NvRegPowerState2);
1105 u8 __iomem *base = get_hwbase(dev);
1107 writel(mask, base + NvRegIrqMask);
1113 u8 __iomem *base = get_hwbase(dev);
1116 writel(mask, base + NvRegIrqMask);
1119 writel(0, base + NvRegMSIIrqMask);
1120 writel(0, base + NvRegIrqMask);
1145 u8 __iomem *base = get_hwbase(dev);
1149 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1151 reg = readl(base + NvRegMIIControl);
1153 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1159 writel(value, base + NvRegMIIData);
1162 writel(reg, base + NvRegMIIControl);
1170 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1173 retval = readl(base + NvRegMIIData);
1230 u8 __iomem *base = get_hwbase(dev);
1231 u32 powerstate = readl(base + NvRegPowerState2);
1235 writel(powerstate, base + NvRegPowerState2);
1239 writel(powerstate, base + NvRegPowerState2);
1390 u8 __iomem *base = get_hwbase(dev);
1440 phyinterface = readl(base + NvRegPhyInterface);
1535 u8 __iomem *base = get_hwbase(dev);
1536 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1539 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1541 writel(rx_ctrl, base + NvRegReceiverControl);
1542 pci_push(base);
1544 writel(np->linkspeed, base + NvRegLinkSpeed);
1545 pci_push(base);
1549 writel(rx_ctrl, base + NvRegReceiverControl);
1550 pci_push(base);
1556 u8 __iomem *base = get_hwbase(dev);
1557 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1563 writel(rx_ctrl, base + NvRegReceiverControl);
1571 writel(0, base + NvRegLinkSpeed);
1577 u8 __iomem *base = get_hwbase(dev);
1578 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1583 writel(tx_ctrl, base + NvRegTransmitterControl);
1584 pci_push(base);
1590 u8 __iomem *base = get_hwbase(dev);
1591 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1597 writel(tx_ctrl, base + NvRegTransmitterControl);
1605 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1606 base + NvRegTransmitPoll);
1624 u8 __iomem *base = get_hwbase(dev);
1626 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1627 pci_push(base);
1629 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1630 pci_push(base);
1636 u8 __iomem *base = get_hwbase(dev);
1639 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1640 pci_push(base);
1643 temp1 = readl(base + NvRegMacAddrA);
1644 temp2 = readl(base + NvRegMacAddrB);
1645 temp3 = readl(base + NvRegTransmitPoll);
1647 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1648 pci_push(base);
1650 writel(0, base + NvRegMacReset);
1651 pci_push(base);
1655 writel(temp1, base + NvRegMacAddrA);
1656 writel(temp2, base + NvRegMacAddrB);
1657 writel(temp3, base + NvRegTransmitPoll);
1659 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1660 pci_push(base);
1667 u8 __iomem *base = get_hwbase(dev);
1676 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1677 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1678 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1679 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1680 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1681 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1682 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1683 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1684 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1685 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1686 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1687 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1688 np->estats.rx_runt += readl(base + NvRegRxRunt);
1689 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1690 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1691 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1692 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1693 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1694 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1695 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1696 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1717 np->estats.tx_deferral += readl(base + NvRegTxDef);
1718 np->estats.tx_packets += readl(base + NvRegTxFrame);
1719 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1720 np->estats.tx_pause += readl(base + NvRegTxPause);
1721 np->estats.rx_pause += readl(base + NvRegRxPause);
1722 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1727 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1728 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1729 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
2100 u8 __iomem *base = get_hwbase(dev);
2105 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2112 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2116 writel(reg, base + NvRegSlotTime);
2149 u8 __iomem *base = get_hwbase(dev);
2193 writel(temp, base + NvRegBackOffControl);
2202 writel(temp, base + NvRegBackOffControl);
2745 u8 __iomem *base = get_hwbase(dev);
2751 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2753 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2767 readl(base + i + 0), readl(base + i + 4),
2768 readl(base + i + 8), readl(base + i + 12),
2769 readl(base + i + 16), readl(base + i + 20),
2770 readl(base + i + 24), readl(base + i + 28));
3114 u8 __iomem *base = get_hwbase(dev);
3138 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3141 base + NvRegRingSizes);
3142 pci_push(base);
3144 pci_push(base);
3159 u8 __iomem *base = get_hwbase(dev);
3166 writel(mac[0], base + NvRegMacAddrA);
3167 writel(mac[1], base + NvRegMacAddrB);
3214 u8 __iomem *base = get_hwbase(dev);
3217 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3262 writel(addr[0], base + NvRegMulticastAddrA);
3263 writel(addr[1], base + NvRegMulticastAddrB);
3264 writel(mask[0], base + NvRegMulticastMaskA);
3265 writel(mask[1], base + NvRegMulticastMaskB);
3266 writel(pff, base + NvRegPacketFilterFlags);
3274 u8 __iomem *base = get_hwbase(dev);
3279 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3281 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3284 writel(pff, base + NvRegPacketFilterFlags);
3288 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3296 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3298 writel(pause_enable, base + NvRegTxPauseFrame);
3299 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3302 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3303 writel(regmisc, base + NvRegMisc1);
3311 u8 __iomem *base = get_hwbase(dev);
3322 phyreg = readl(base + NvRegSlotTime);
3330 writel(phyreg, base + NvRegSlotTime);
3333 phyreg = readl(base + NvRegPhyInterface);
3342 writel(phyreg, base + NvRegPhyInterface);
3353 writel(txreg, base + NvRegTxDeferral);
3364 writel(txreg, base + NvRegTxWatermark);
3367 base + NvRegMisc1);
3368 pci_push(base);
3369 writel(np->linkspeed, base + NvRegLinkSpeed);
3370 pci_push(base);
3387 u8 __iomem *base = get_hwbase(dev);
3495 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3499 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3505 phyreg = readl(base + NvRegSlotTime);
3512 writel(phyreg, base + NvRegSlotTime);
3515 phyreg = readl(base + NvRegPhyInterface);
3523 writel(phyreg, base + NvRegPhyInterface);
3545 writel(txreg, base + NvRegTxDeferral);
3555 writel(txreg, base + NvRegTxWatermark);
3558 base + NvRegMisc1);
3559 pci_push(base);
3560 writel(np->linkspeed, base + NvRegLinkSpeed);
3561 pci_push(base);
3627 u8 __iomem *base = get_hwbase(dev);
3630 miistat = readl(base + NvRegMIIStatus);
3631 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3644 u8 __iomem *base = np->base;
3646 writel(0, base + NvRegMSIIrqMask);
3647 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3683 u8 __iomem *base = get_hwbase(dev);
3686 np->events = readl(base + NvRegIrqStatus);
3687 writel(np->events, base + NvRegIrqStatus);
3689 np->events = readl(base + NvRegMSIXIrqStatus);
3690 writel(np->events, base + NvRegMSIXIrqStatus);
3701 writel(0, base + NvRegIrqMask);
3716 u8 __iomem *base = get_hwbase(dev);
3719 np->events = readl(base + NvRegIrqStatus);
3720 writel(np->events, base + NvRegIrqStatus);
3722 np->events = readl(base + NvRegMSIXIrqStatus);
3723 writel(np->events, base + NvRegMSIXIrqStatus);
3734 writel(0, base + NvRegIrqMask);
3745 u8 __iomem *base = get_hwbase(dev);
3751 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3752 writel(events, base + NvRegMSIXIrqStatus);
3764 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3765 pci_push(base);
3786 u8 __iomem *base = get_hwbase(dev);
3848 writel(np->irqmask, base + NvRegIrqMask);
3857 u8 __iomem *base = get_hwbase(dev);
3863 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3864 writel(events, base + NvRegMSIXIrqStatus);
3881 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3882 pci_push(base);
3902 u8 __iomem *base = get_hwbase(dev);
3908 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3909 writel(events, base + NvRegMSIXIrqStatus);
3933 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3934 pci_push(base);
3947 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3948 pci_push(base);
3969 u8 __iomem *base = get_hwbase(dev);
3973 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3974 writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3976 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3977 writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3979 pci_push(base);
3994 u8 __iomem *base = get_hwbase(dev);
4006 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
4013 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
4019 u8 __iomem *base = get_hwbase(dev);
4080 writel(0, base + NvRegMSIXMap0);
4081 writel(0, base + NvRegMSIXMap1);
4099 writel(0, base + NvRegMSIXMap0);
4100 writel(0, base + NvRegMSIXMap1);
4120 writel(0, base + NvRegMSIMap0);
4121 writel(0, base + NvRegMSIMap1);
4123 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
4164 u8 __iomem *base = get_hwbase(dev);
4220 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4223 base + NvRegRingSizes);
4224 pci_push(base);
4226 pci_push(base);
4229 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4231 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4241 writel(mask, base + NvRegIrqMask);
4242 pci_push(base);
4318 u8 __iomem *base = get_hwbase(dev);
4329 writel(flags, base + NvRegWakeUpFlags);
4344 cmd->base.port = PORT_MII;
4370 cmd->base.duplex = DUPLEX_HALF;
4372 cmd->base.duplex = DUPLEX_FULL;
4375 cmd->base.duplex = DUPLEX_UNKNOWN;
4377 cmd->base.speed = speed;
4378 cmd->base.autoneg = np->autoneg;
4405 cmd->base.phy_address = np->phyaddr;
4421 u32 speed = cmd->base.speed;
4427 if (cmd->base.port != PORT_MII)
4429 if (cmd->base.phy_address != np->phyaddr) {
4434 if (cmd->base.autoneg == AUTONEG_ENABLE) {
4445 } else if (cmd->base.autoneg == AUTONEG_DISABLE) {
4451 if (cmd->base.duplex != DUPLEX_HALF &&
4452 cmd->base.duplex != DUPLEX_FULL)
4482 if (cmd->base.autoneg == AUTONEG_ENABLE) {
4534 if (speed == SPEED_10 && cmd->base.duplex == DUPLEX_HALF)
4536 if (speed == SPEED_10 && cmd->base.duplex == DUPLEX_FULL)
4538 if (speed == SPEED_100 && cmd->base.duplex == DUPLEX_HALF)
4540 if (speed == SPEED_100 && cmd->base.duplex == DUPLEX_FULL)
4601 u8 __iomem *base = get_hwbase(dev);
4608 rbuf[i] = readl(base + i*sizeof(u32));
4673 u8 __iomem *base = get_hwbase(dev);
4773 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4776 base + NvRegRingSizes);
4777 pci_push(base);
4779 pci_push(base);
4962 u8 __iomem *base = get_hwbase(dev);
4981 writel(np->txrxctl_bits, base + NvRegTxRxControl);
5047 u8 __iomem *base = get_hwbase(dev);
5052 orig_read = readl(base + nv_registers_test[i].reg);
5057 writel(orig_read, base + nv_registers_test[i].reg);
5059 new_read = readl(base + nv_registers_test[i].reg);
5066 writel(orig_read, base + nv_registers_test[i].reg);
5076 u8 __iomem *base = get_hwbase(dev);
5084 save_poll_interval = readl(base+NvRegPollingInterval);
5098 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5099 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5115 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5117 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5126 writel(save_poll_interval, base + NvRegPollingInterval);
5127 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5139 u8 __iomem *base = get_hwbase(dev);
5152 filter_flags = readl(base + NvRegPacketFilterFlags);
5153 misc1_flags = readl(base + NvRegMisc1);
5163 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
5164 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
5167 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5170 base + NvRegRingSizes);
5171 pci_push(base);
5254 writel(misc1_flags, base + NvRegMisc1);
5255 writel(filter_flags, base + NvRegPacketFilterFlags);
5265 u8 __iomem *base = get_hwbase(dev);
5285 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5287 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5326 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5329 base + NvRegRingSizes);
5330 pci_push(base);
5332 pci_push(base);
5379 u8 __iomem *base = get_hwbase(dev);
5384 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5394 tx_ctrl = readl(base + NvRegTransmitterControl);
5396 writel(tx_ctrl, base + NvRegTransmitterControl);
5399 tx_ctrl = readl(base + NvRegTransmitterControl);
5414 u8 __iomem *base = get_hwbase(dev);
5419 tx_ctrl = readl(base + NvRegTransmitterControl);
5421 writel(tx_ctrl, base + NvRegTransmitterControl);
5430 u8 __iomem *base = get_hwbase(dev);
5431 u32 data_ready = readl(base + NvRegTransmitterControl);
5436 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5437 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5440 data_ready2 = readl(base + NvRegTransmitterControl);
5451 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5459 u8 __iomem *base = get_hwbase(dev);
5472 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5473 writel(0, base + NvRegMulticastAddrB);
5474 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5475 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5476 writel(0, base + NvRegPacketFilterFlags);
5478 writel(0, base + NvRegTransmitterControl);
5479 writel(0, base + NvRegReceiverControl);
5481 writel(0, base + NvRegAdapterControl);
5484 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5490 writel(0, base + NvRegLinkSpeed);
5491 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5493 writel(0, base + NvRegUnknownSetupReg6);
5500 base + NvRegRingSizes);
5502 writel(np->linkspeed, base + NvRegLinkSpeed);
5504 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5506 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5507 writel(np->txrxctl_bits, base + NvRegTxRxControl);
5508 writel(np->vlanctl_bits, base + NvRegVlanControl);
5509 pci_push(base);
5510 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5517 writel(0, base + NvRegMIIMask);
5518 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5519 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5521 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5522 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5523 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5524 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5526 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5531 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5535 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5537 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5541 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5542 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5545 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5547 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5549 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5550 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5552 base + NvRegAdapterControl);
5553 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5554 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5556 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5558 i = readl(base + NvRegPowerState);
5560 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5562 pci_push(base);
5564 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5567 pci_push(base);
5568 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5569 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5570 pci_push(base);
5579 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5580 writel(0, base + NvRegMulticastAddrB);
5581 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5582 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5583 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5587 readl(base + NvRegMIIStatus);
5588 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5629 u8 __iomem *base;
5648 base = get_hwbase(dev);
5650 pci_push(base);
5660 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5713 u8 __iomem *base;
5844 np->base = ioremap(addr, np->register_size);
5845 if (!np->base)
5888 base = get_hwbase(dev);
5889 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5890 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5893 txreg = readl(base + NvRegTransmitPoll);
5926 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5949 writel(0, base + NvRegWakeUpFlags);
5956 powerstate = readl(base + NvRegPowerState2);
5961 writel(powerstate, base + NvRegPowerState2);
6017 writel(0, base + NvRegMIIMask);
6018 phystate = readl(base + NvRegAdapterControl);
6022 writel(phystate, base + NvRegAdapterControl);
6024 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
6028 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
6029 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
6034 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
6037 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
6143 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
6186 u8 __iomem *base = get_hwbase(dev);
6191 writel(np->orig_mac[0], base + NvRegMacAddrA);
6192 writel(np->orig_mac[1], base + NvRegMacAddrB);
6193 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
6194 base + NvRegTransmitPoll);
6226 u8 __iomem *base = get_hwbase(dev);
6237 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6247 u8 __iomem *base = get_hwbase(dev);
6252 writel(np->saved_config_space[i], base+i*sizeof(u32));