Lines Matching defs:bmcr
1477 * (certain phys need bmcr to be setup with reset)
3394 u32 bmcr;
3403 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3404 if (bmcr & BMCR_LOOPBACK) {
4483 int adv, bmcr;
4514 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4516 bmcr |= BMCR_ANENABLE;
4519 if (phy_reset(dev, bmcr)) {
4524 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4525 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4528 int adv, bmcr;
4560 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4561 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4563 bmcr |= BMCR_FULLDPLX;
4565 bmcr |= BMCR_SPEED100;
4568 if (phy_reset(dev, bmcr)) {
4573 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4618 int bmcr;
4634 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4636 bmcr |= BMCR_ANENABLE;
4638 if (phy_reset(dev, bmcr)) {
4643 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4644 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4806 int adv, bmcr;
4850 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4851 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4852 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);