Lines Matching refs:dtr
323 static inline void vxge_re_pre_post(void *dtr, struct vxge_ring *ring,
329 vxge_hw_ring_rxd_1b_set(dtr, rx_priv->data_dma, rx_priv->data_size);
330 vxge_hw_ring_rxd_pre_post(ring->handle, dtr);
354 vxge_rx_1b_compl(struct __vxge_hw_ring *ringh, void *dtr,
375 prefetch((char *)dtr + L1_CACHE_BYTES);
376 rx_priv = vxge_hw_ring_rxd_private_get(dtr);
386 vxge_hw_ring_rxd_1b_get(ringh, dtr, &dma_sizes);
395 vxge_hw_ring_rxd_1b_info_get(ringh, dtr, &ext_info);
402 if (vxge_hw_ring_handle_tcode(ringh, dtr, t_code) !=
415 vxge_re_pre_post(dtr, ring, rx_priv);
417 vxge_post(&dtr_cnt, &first_dtr, dtr, ringh);
424 if (vxge_rx_alloc(dtr, ring, data_size) != NULL) {
425 if (!vxge_rx_map(dtr, ring)) {
432 vxge_hw_ring_rxd_pre_post(ringh, dtr);
433 vxge_post(&dtr_cnt, &first_dtr, dtr,
439 vxge_re_pre_post(dtr, ring, rx_priv);
441 vxge_post(&dtr_cnt, &first_dtr, dtr,
447 vxge_re_pre_post(dtr, ring, rx_priv);
449 vxge_post(&dtr_cnt, &first_dtr, dtr, ringh);
472 vxge_re_pre_post(dtr, ring, rx_priv);
474 vxge_post(&dtr_cnt, &first_dtr, dtr,
480 vxge_re_pre_post(dtr, ring, rx_priv);
482 vxge_post(&dtr_cnt, &first_dtr, dtr, ringh);
525 } while (vxge_hw_ring_rxd_next_completed(ringh, &dtr,
547 vxge_xmit_compl(struct __vxge_hw_fifo *fifo_hw, void *dtr,
563 vxge_hw_fifo_txdl_private_get(dtr);
570 "%s: %s:%d fifo_hw = %p dtr = %p "
572 __LINE__, fifo_hw, dtr, t_code);
582 "%s: tx: dtr %p completed due to "
584 dtr, t_code);
585 vxge_hw_fifo_handle_tcode(fifo_hw, dtr, t_code);
599 vxge_hw_fifo_txdl_free(fifo_hw, dtr);
619 &dtr, &t_code) == VXGE_HW_OK);
808 void *dtr = NULL;
881 status = vxge_hw_fifo_txdl_reserve(fifo_hw, &dtr, &dtr_priv);
890 "%s: %s:%d fifo_hw = %p dtr = %p dtr_priv = %p",
892 fifo_hw, dtr, dtr_priv);
896 vxge_hw_fifo_txdl_vlan_set(dtr, vlan_tag);
905 vxge_hw_fifo_txdl_free(fifo_hw, dtr);
910 txdl_priv = vxge_hw_fifo_txdl_private_get(dtr);
921 vxge_hw_fifo_txdl_buffer_set(fifo_hw, dtr, j++, dma_pointer,
942 vxge_hw_fifo_txdl_buffer_set(fifo_hw, dtr, j++, dma_pointer,
954 vxge_hw_fifo_txdl_mss_set(dtr, mss);
964 vxge_hw_fifo_txdl_cksum_set_bits(dtr,
969 vxge_hw_fifo_txdl_post(fifo_hw, dtr);
990 vxge_hw_fifo_txdl_free(fifo_hw, dtr);