Lines Matching defs:fifo

1226  * __vxge_hw_device_fifo_config_check - Check fifo configuration.
1227 * Check the fifo configuration
1252 status = __vxge_hw_device_fifo_config_check(&vp_config->fifo);
1366 if (device_config->vp_config[i].fifo.enable ==
1368 nblocks += device_config->vp_config[i].fifo.fifo_blocks;
2932 device_config->vp_config[i].fifo.enable = VXGE_HW_FIFO_ENABLE;
2934 device_config->vp_config[i].fifo.fifo_blocks =
2937 device_config->vp_config[i].fifo.max_frags =
2940 device_config->vp_config[i].fifo.memblock_size =
2943 device_config->vp_config[i].fifo.alignment_size =
2946 device_config->vp_config[i].fifo.intr =
2949 device_config->vp_config[i].fifo.no_snoop_bits =
3326 * This function terminates the TxDs of fifo
3328 static enum vxge_hw_status __vxge_hw_fifo_abort(struct __vxge_hw_fifo *fifo)
3333 vxge_hw_channel_dtr_try_complete(&fifo->channel, &txdlh);
3338 vxge_hw_channel_dtr_complete(&fifo->channel);
3340 if (fifo->txdl_term) {
3341 fifo->txdl_term(txdlh,
3343 fifo->channel.userdata);
3346 vxge_hw_channel_dtr_free(&fifo->channel, txdlh);
3353 * __vxge_hw_fifo_reset - Resets the fifo
3354 * This function resets the fifo during vpath reset operation
3356 static enum vxge_hw_status __vxge_hw_fifo_reset(struct __vxge_hw_fifo *fifo)
3360 __vxge_hw_fifo_abort(fifo);
3361 status = __vxge_hw_channel_reset(&fifo->channel);
3373 struct __vxge_hw_fifo *fifo = vp->vpath->fifoh;
3375 __vxge_hw_fifo_abort(fifo);
3377 if (fifo->mempool)
3378 __vxge_hw_mempool_destroy(fifo->mempool);
3382 __vxge_hw_channel_free(&fifo->channel);
3403 struct __vxge_hw_fifo *fifo =
3413 txdl_priv = __vxge_hw_fifo_txdl_priv(fifo, txdp);
3417 fifo->channel.reserve_arr[fifo->channel.reserve_ptr - 1 - index] = txdp;
3438 struct __vxge_hw_fifo *fifo;
3449 config = &vpath->hldev->config.vp_config[vpath->vp_id].fifo;
3455 fifo = (struct __vxge_hw_fifo *)__vxge_hw_channel_allocate(vp,
3460 if (fifo == NULL) {
3465 vpath->fifoh = fifo;
3466 fifo->nofl_db = vpath->nofl_db;
3468 fifo->vp_id = vpath->vp_id;
3469 fifo->vp_reg = vpath->vp_reg;
3470 fifo->stats = &vpath->sw_stats->fifo_stats;
3472 fifo->config = config;
3475 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_UTILZ;
3476 fifo->tim_tti_cfg1_saved = vpath->tim_tti_cfg1_saved;
3477 fifo->tim_tti_cfg3_saved = vpath->tim_tti_cfg3_saved;
3479 if (fifo->config->intr)
3480 fifo->interrupt_type = VXGE_HW_FIFO_TXD_INT_TYPE_PER_LIST;
3482 fifo->no_snoop_bits = config->no_snoop_bits;
3504 fifo->priv_size =
3506 fifo->priv_size = ((fifo->priv_size + VXGE_CACHE_LINE_SIZE - 1) /
3509 fifo->per_txdl_space = attr->per_txdl_space;
3512 fifo->txdl_size = txdl_size;
3513 fifo->txdl_per_memblock = txdl_per_memblock;
3515 fifo->txdl_term = attr->txdl_term;
3516 fifo->callback = attr->callback;
3518 if (fifo->txdl_per_memblock == 0) {
3526 fifo->mempool =
3528 fifo->config->memblock_size,
3529 fifo->txdl_size,
3530 fifo->priv_size,
3531 (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
3532 (fifo->config->fifo_blocks * fifo->txdl_per_memblock),
3534 fifo);
3536 if (fifo->mempool == NULL) {
3542 status = __vxge_hw_channel_initialize(&fifo->channel);
3548 vxge_assert(fifo->channel.reserve_ptr);
4153 if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4158 ((vpath->vp_config->fifo.memblock_size /
4159 (vpath->vp_config->fifo.max_frags *
4161 vpath->vp_config->fifo.fifo_blocks)) {
4297 if (config->fifo.enable == VXGE_HW_FIFO_ENABLE) {
4817 if (vpath->vp_config->fifo.enable == VXGE_HW_FIFO_ENABLE) {