Lines Matching defs:data0
158 u32 fw_memo, u32 offset, u64 *data0, u64 *data1,
172 writeq(*data0, &vp_reg->rts_access_steer_data0);
209 *data0 = readq(&vp_reg->rts_access_steer_data0);
225 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
235 &data0, &data1, &steer_ctrl);
239 *major = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
240 *minor = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
241 *build = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
248 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
259 &data0, &data1, &steer_ctrl);
279 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
291 &data0, &data1, &steer_ctrl);
303 data0 = *((u64 *)fwdata);
310 &data0, &data1, &steer_ctrl);
317 ret_code = VXGE_HW_UPGRADE_GET_RET_ERR_CODE(data0);
324 fwdata += (data0 >> 8) & 0xFFFFFFFF;
329 sec_code = VXGE_HW_UPGRADE_GET_SEC_ERR_CODE(data0);
376 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
384 data0 = VXGE_HW_RTS_ACCESS_STEER_ROM_IMAGE_INDEX(i);
390 0, &data0, &data1, &steer_ctrl);
394 img[i].is_valid = VXGE_HW_GET_EPROM_IMAGE_VALID(data0);
395 img[i].index = VXGE_HW_GET_EPROM_IMAGE_INDEX(data0);
396 img[i].type = VXGE_HW_GET_EPROM_IMAGE_TYPE(data0);
397 img[i].version = VXGE_HW_GET_EPROM_IMAGE_REV(data0);
811 u64 data0 = 0, data1 = 0, steer_ctrl = 0;
817 0, &data0, &data1, &steer_ctrl);
822 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_DAY(data0);
824 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MONTH(data0);
826 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_YEAR(data0);
832 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MAJOR(data0);
834 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_MINOR(data0);
836 (u32) VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_FW_VER_BUILD(data0);
875 u64 data0, data1 = 0, steer_ctrl = 0;
881 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_SERIAL_NUMBER;
886 0, &data0, &data1, &steer_ctrl);
890 ((u64 *)serial_number)[0] = be64_to_cpu(data0);
893 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_MEMO_ITEM_PART_NUMBER;
899 0, &data0, &data1, &steer_ctrl);
903 ((u64 *)part_number)[0] = be64_to_cpu(data0);
908 data0 = i;
914 0, &data0, &data1, &steer_ctrl);
918 ((u64 *)product_desc)[j++] = be64_to_cpu(data0);
933 u64 data0, data1 = 0, steer_ctrl = 0;
936 data0 = 0;
941 0, &data0, &data1, &steer_ctrl);
945 hw_info->function_mode = VXGE_HW_GET_FUNC_MODE_VAL(data0);
958 data0 = 0, data1 = 0, steer_ctrl = 0;
965 0, &data0, &data1, &steer_ctrl);
969 data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_DA_MAC_ADDR(data0);
974 macaddr[i - 1] = (u8) (data0 & 0xFF);
975 data0 >>= 8;
982 data0 = 0, data1 = 0, steer_ctrl = 0;
3606 u64 data0, data1 = 0, steer_ctrl = 0;
3616 data0 = on_off;
3620 0, &data0, &data1, &steer_ctrl);
3631 u64 *data0, u64 *data1)
3653 data0, data1, &steer_ctrl);
3673 u64 data0, data1 = 0, steer_ctrl = 0;
3681 data0 = steer_data0;
3689 &data0, &data1, &steer_ctrl);
3703 u64 data0, data1;
3714 0, &data0, &data1);
3718 data0 &= ~(VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_BUCKET_SIZE(0xf) |
3721 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_EN |
3726 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV4_EN;
3729 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV4_EN;
3732 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_TCP_IPV6_EN;
3735 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EN;
3738 data0 |=
3742 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_RTH_IPV6_EX_EN;
3744 if (VXGE_HW_RTS_ACCESS_STEER_DATA0_GET_RTH_GEN_ACTIVE_TABLE(data0))
3745 data0 &= ~VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3747 data0 |= VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_GEN_ACTIVE_TABLE;
3752 0, data0, 0);
3758 vxge_hw_rts_rth_data0_data1_get(u32 j, u64 *data0, u64 *data1,
3763 *data0 = VXGE_HW_RTS_ACCESS_STEER_DATA0_RTH_ITEM0_BUCKET_NUM(j)|
3769 *data0 |=
3802 u64 data0;
3825 data0 =
3830 action, rts_table, j, data0, data1);
3840 data0 =
3847 rts_table, j, data0, data1);
3860 data0 = 0;
3869 &data0, &data1, 1, itable);
3880 &data0, &data1, 2, itable);
3891 &data0, &data1, 3, itable);
3902 &data0, &data1, 4, itable);
3907 if (data0 != 0) {
3911 0, data0, data1);