Lines Matching refs:bar0
1009 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1013 val64 = readq(&bar0->pci_mode);
1043 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1049 val64 = readq(&bar0->pci_mode);
1111 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1135 writeq(val64, &bar0->tti_data1_mem);
1160 writeq(val64, &bar0->tti_data2_mem);
1165 writeq(val64, &bar0->tti_command_mem);
1167 if (wait_for_cmd_complete(&bar0->tti_command_mem,
1187 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1210 writeq(val64, &bar0->sw_reset);
1212 val64 = readq(&bar0->sw_reset);
1217 writeq(val64, &bar0->sw_reset);
1219 val64 = readq(&bar0->sw_reset);
1226 val64 = readq(&bar0->adapter_status);
1236 add = &bar0->mac_cfg;
1237 val64 = readq(&bar0->mac_cfg);
1239 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1241 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1245 val64 = readq(&bar0->mac_int_mask);
1246 val64 = readq(&bar0->mc_int_mask);
1247 val64 = readq(&bar0->xgxs_int_mask);
1251 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1256 &bar0->dtx_control, UF);
1264 &bar0->dtx_control, UF);
1265 val64 = readq(&bar0->dtx_control);
1272 writeq(val64, &bar0->tx_fifo_partition_0);
1273 writeq(val64, &bar0->tx_fifo_partition_1);
1274 writeq(val64, &bar0->tx_fifo_partition_2);
1275 writeq(val64, &bar0->tx_fifo_partition_3);
1290 writeq(val64, &bar0->tx_fifo_partition_0);
1295 writeq(val64, &bar0->tx_fifo_partition_1);
1300 writeq(val64, &bar0->tx_fifo_partition_2);
1305 writeq(val64, &bar0->tx_fifo_partition_3);
1320 writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1322 val64 = readq(&bar0->tx_fifo_partition_0);
1324 &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1330 val64 = readq(&bar0->tx_pa_cfg);
1335 writeq(val64, &bar0->tx_pa_cfg);
1344 writeq(val64, &bar0->rx_queue_priority);
1393 writeq(val64, &bar0->rx_queue_cfg);
1402 writeq(val64, &bar0->tx_w_round_robin_0);
1403 writeq(val64, &bar0->tx_w_round_robin_1);
1404 writeq(val64, &bar0->tx_w_round_robin_2);
1405 writeq(val64, &bar0->tx_w_round_robin_3);
1406 writeq(val64, &bar0->tx_w_round_robin_4);
1410 writeq(val64, &bar0->tx_w_round_robin_0);
1411 writeq(val64, &bar0->tx_w_round_robin_1);
1412 writeq(val64, &bar0->tx_w_round_robin_2);
1413 writeq(val64, &bar0->tx_w_round_robin_3);
1415 writeq(val64, &bar0->tx_w_round_robin_4);
1419 writeq(val64, &bar0->tx_w_round_robin_0);
1421 writeq(val64, &bar0->tx_w_round_robin_1);
1423 writeq(val64, &bar0->tx_w_round_robin_2);
1425 writeq(val64, &bar0->tx_w_round_robin_3);
1427 writeq(val64, &bar0->tx_w_round_robin_4);
1431 writeq(val64, &bar0->tx_w_round_robin_0);
1432 writeq(val64, &bar0->tx_w_round_robin_1);
1433 writeq(val64, &bar0->tx_w_round_robin_2);
1434 writeq(val64, &bar0->tx_w_round_robin_3);
1436 writeq(val64, &bar0->tx_w_round_robin_4);
1440 writeq(val64, &bar0->tx_w_round_robin_0);
1442 writeq(val64, &bar0->tx_w_round_robin_1);
1444 writeq(val64, &bar0->tx_w_round_robin_2);
1446 writeq(val64, &bar0->tx_w_round_robin_3);
1448 writeq(val64, &bar0->tx_w_round_robin_4);
1452 writeq(val64, &bar0->tx_w_round_robin_0);
1454 writeq(val64, &bar0->tx_w_round_robin_1);
1456 writeq(val64, &bar0->tx_w_round_robin_2);
1458 writeq(val64, &bar0->tx_w_round_robin_3);
1460 writeq(val64, &bar0->tx_w_round_robin_4);
1464 writeq(val64, &bar0->tx_w_round_robin_0);
1466 writeq(val64, &bar0->tx_w_round_robin_1);
1468 writeq(val64, &bar0->tx_w_round_robin_2);
1470 writeq(val64, &bar0->tx_w_round_robin_3);
1472 writeq(val64, &bar0->tx_w_round_robin_4);
1476 writeq(val64, &bar0->tx_w_round_robin_0);
1477 writeq(val64, &bar0->tx_w_round_robin_1);
1478 writeq(val64, &bar0->tx_w_round_robin_2);
1479 writeq(val64, &bar0->tx_w_round_robin_3);
1481 writeq(val64, &bar0->tx_w_round_robin_4);
1486 val64 = readq(&bar0->tx_fifo_partition_0);
1488 writeq(val64, &bar0->tx_fifo_partition_0);
1497 writeq(val64, &bar0->rx_w_round_robin_0);
1498 writeq(val64, &bar0->rx_w_round_robin_1);
1499 writeq(val64, &bar0->rx_w_round_robin_2);
1500 writeq(val64, &bar0->rx_w_round_robin_3);
1501 writeq(val64, &bar0->rx_w_round_robin_4);
1504 writeq(val64, &bar0->rts_qos_steering);
1508 writeq(val64, &bar0->rx_w_round_robin_0);
1509 writeq(val64, &bar0->rx_w_round_robin_1);
1510 writeq(val64, &bar0->rx_w_round_robin_2);
1511 writeq(val64, &bar0->rx_w_round_robin_3);
1513 writeq(val64, &bar0->rx_w_round_robin_4);
1516 writeq(val64, &bar0->rts_qos_steering);
1520 writeq(val64, &bar0->rx_w_round_robin_0);
1522 writeq(val64, &bar0->rx_w_round_robin_1);
1524 writeq(val64, &bar0->rx_w_round_robin_2);
1526 writeq(val64, &bar0->rx_w_round_robin_3);
1528 writeq(val64, &bar0->rx_w_round_robin_4);
1531 writeq(val64, &bar0->rts_qos_steering);
1535 writeq(val64, &bar0->rx_w_round_robin_0);
1536 writeq(val64, &bar0->rx_w_round_robin_1);
1537 writeq(val64, &bar0->rx_w_round_robin_2);
1538 writeq(val64, &bar0->rx_w_round_robin_3);
1540 writeq(val64, &bar0->rx_w_round_robin_4);
1543 writeq(val64, &bar0->rts_qos_steering);
1547 writeq(val64, &bar0->rx_w_round_robin_0);
1549 writeq(val64, &bar0->rx_w_round_robin_1);
1551 writeq(val64, &bar0->rx_w_round_robin_2);
1553 writeq(val64, &bar0->rx_w_round_robin_3);
1555 writeq(val64, &bar0->rx_w_round_robin_4);
1558 writeq(val64, &bar0->rts_qos_steering);
1562 writeq(val64, &bar0->rx_w_round_robin_0);
1564 writeq(val64, &bar0->rx_w_round_robin_1);
1566 writeq(val64, &bar0->rx_w_round_robin_2);
1568 writeq(val64, &bar0->rx_w_round_robin_3);
1570 writeq(val64, &bar0->rx_w_round_robin_4);
1573 writeq(val64, &bar0->rts_qos_steering);
1577 writeq(val64, &bar0->rx_w_round_robin_0);
1579 writeq(val64, &bar0->rx_w_round_robin_1);
1581 writeq(val64, &bar0->rx_w_round_robin_2);
1583 writeq(val64, &bar0->rx_w_round_robin_3);
1585 writeq(val64, &bar0->rx_w_round_robin_4);
1588 writeq(val64, &bar0->rts_qos_steering);
1592 writeq(val64, &bar0->rx_w_round_robin_0);
1593 writeq(val64, &bar0->rx_w_round_robin_1);
1594 writeq(val64, &bar0->rx_w_round_robin_2);
1595 writeq(val64, &bar0->rx_w_round_robin_3);
1597 writeq(val64, &bar0->rx_w_round_robin_4);
1600 writeq(val64, &bar0->rts_qos_steering);
1607 writeq(val64, &bar0->rts_frm_len_n[i]);
1612 writeq(val64, &bar0->rts_frm_len_n[i]);
1626 &bar0->rts_frm_len_n[i]);
1641 writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1645 writeq(val64, &bar0->stat_byte_cnt);
1654 writeq(val64, &bar0->mac_link_util);
1680 writeq(val64, &bar0->rti_data1_mem);
1690 writeq(val64, &bar0->rti_data2_mem);
1696 writeq(val64, &bar0->rti_command_mem);
1707 val64 = readq(&bar0->rti_command_mem);
1725 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1726 writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1729 add = &bar0->mac_cfg;
1730 val64 = readq(&bar0->mac_cfg);
1732 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1734 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1736 val64 = readq(&bar0->mac_cfg);
1739 add = &bar0->mac_cfg;
1740 val64 = readq(&bar0->mac_cfg);
1743 writeq(val64, &bar0->mac_cfg);
1745 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1747 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1755 val64 = readq(&bar0->rmac_pause_cfg);
1758 writeq(val64, &bar0->rmac_pause_cfg);
1772 writeq(val64, &bar0->mc_pause_thresh_q0q3);
1780 writeq(val64, &bar0->mc_pause_thresh_q4q7);
1786 val64 = readq(&bar0->pic_control);
1788 writeq(val64, &bar0->pic_control);
1791 writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1792 writeq(0x0, &bar0->read_retry_delay);
1793 writeq(0x0, &bar0->write_retry_delay);
1803 writeq(val64, &bar0->misc_control);
1804 val64 = readq(&bar0->pic_control2);
1806 writeq(val64, &bar0->pic_control2);
1810 writeq(val64, &bar0->tmac_avg_ipg);
1850 struct XENA_dev_config __iomem *bar0 = nic->bar0;
1854 writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1861 TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1866 &bar0->pfc_err_mask);
1870 TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1878 flag, &bar0->pcc_err_mask);
1881 TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1886 flag, &bar0->lso_err_mask);
1889 flag, &bar0->tpa_err_mask);
1891 do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1897 &bar0->mac_int_mask);
1901 flag, &bar0->mac_tmac_err_mask);
1907 &bar0->xgxs_int_mask);
1910 flag, &bar0->xgxs_txgxs_err_mask);
1917 flag, &bar0->rxdma_int_mask);
1921 RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1925 &bar0->prc_pcix_err_mask);
1928 &bar0->rpa_err_mask);
1934 flag, &bar0->rda_err_mask);
1937 flag, &bar0->rti_err_mask);
1943 &bar0->mac_int_mask);
1950 flag, &bar0->mac_rmac_err_mask);
1956 &bar0->xgxs_int_mask);
1958 &bar0->xgxs_rxgxs_err_mask);
1964 flag, &bar0->mc_int_mask);
1967 &bar0->mc_err_mask);
1988 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2008 &bar0->pic_int_mask);
2010 &bar0->gpio_int_mask);
2012 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2018 writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2030 writeq(0x0, &bar0->tx_traffic_mask);
2036 writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2045 writeq(0x0, &bar0->rx_traffic_mask);
2051 writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2055 temp64 = readq(&bar0->general_int_mask);
2060 writeq(temp64, &bar0->general_int_mask);
2062 nic->general_int_mask = readq(&bar0->general_int_mask);
2076 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2077 u64 val64 = readq(&bar0->adapter_status);
2118 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2119 u64 val64 = readq(&bar0->adapter_status);
2184 struct XENA_dev_config __iomem *bar0 = sp->bar0;
2188 writeq(fix_mac[i++], &bar0->gpio_control);
2190 (void) readq(&bar0->gpio_control);
2209 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2221 &bar0->prc_rxd0_n[i]);
2223 val64 = readq(&bar0->prc_ctrl_n[i]);
2232 writeq(val64, &bar0->prc_ctrl_n[i]);
2237 val64 = readq(&bar0->rx_pa_cfg);
2239 writeq(val64, &bar0->rx_pa_cfg);
2243 val64 = readq(&bar0->rx_pa_cfg);
2245 writeq(val64, &bar0->rx_pa_cfg);
2254 val64 = readq(&bar0->mc_rldram_mrs);
2256 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2257 val64 = readq(&bar0->mc_rldram_mrs);
2262 val64 = readq(&bar0->adapter_control);
2264 writeq(val64, &bar0->adapter_control);
2270 val64 = readq(&bar0->adapter_status);
2287 val64 = readq(&bar0->adapter_control);
2289 writeq(val64, &bar0->adapter_control);
2302 val64 = readq(&bar0->gpio_control);
2304 writeq(val64, &bar0->gpio_control);
2306 writeq(val64, (void __iomem *)bar0 + 0x2700);
2412 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2423 val64 = readq(&bar0->adapter_control);
2425 writeq(val64, &bar0->adapter_control);
2766 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2778 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2792 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2812 writeq(0, &bar0->rx_traffic_mask);
2813 readl(&bar0->rx_traffic_mask);
2832 struct XENA_dev_config __iomem *bar0 = nic->bar0;
2843 writeq(val64, &bar0->rx_traffic_int);
2844 writeq(val64, &bar0->tx_traffic_int);
3088 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3094 writeq(val64, &bar0->mdio_control);
3096 writeq(val64, &bar0->mdio_control);
3105 writeq(val64, &bar0->mdio_control);
3107 writeq(val64, &bar0->mdio_control);
3114 writeq(val64, &bar0->mdio_control);
3116 writeq(val64, &bar0->mdio_control);
3134 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3140 writeq(val64, &bar0->mdio_control);
3142 writeq(val64, &bar0->mdio_control);
3150 writeq(val64, &bar0->mdio_control);
3152 writeq(val64, &bar0->mdio_control);
3156 rval64 = readq(&bar0->mdio_control);
3398 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3415 writeq(val64, &bar0->sw_reset);
3455 writeq(s2BIT(62), &bar0->txpic_int_reg);
3490 val64 = readq(&bar0->gpio_control);
3492 writeq(val64, &bar0->gpio_control);
3494 writeq(val64, (void __iomem *)bar0 + 0x2700);
3502 val64 = readq(&bar0->pcc_err_reg);
3503 writeq(val64, &bar0->pcc_err_reg);
3522 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3530 val64 = readq(&bar0->pif_rd_swapper_fb);
3541 writeq(value[i], &bar0->swapper_ctrl);
3542 val64 = readq(&bar0->pif_rd_swapper_fb);
3555 valr = readq(&bar0->swapper_ctrl);
3559 writeq(valt, &bar0->xmsi_address);
3560 val64 = readq(&bar0->xmsi_address);
3572 writeq((value[i] | valr), &bar0->swapper_ctrl);
3573 writeq(valt, &bar0->xmsi_address);
3574 val64 = readq(&bar0->xmsi_address);
3586 val64 = readq(&bar0->swapper_ctrl);
3607 writeq(val64, &bar0->swapper_ctrl);
3631 writeq(val64, &bar0->swapper_ctrl);
3633 val64 = readq(&bar0->swapper_ctrl);
3639 val64 = readq(&bar0->pif_rd_swapper_fb);
3653 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3658 val64 = readq(&bar0->xmsi_access);
3674 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3683 writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3684 writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3686 writeq(val64, &bar0->xmsi_access);
3695 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3706 writeq(val64, &bar0->xmsi_access);
3712 addr = readq(&bar0->xmsi_address);
3713 data = readq(&bar0->xmsi_data);
3723 struct XENA_dev_config __iomem *bar0 = nic->bar0;
3767 rx_mat = readq(&bar0->rx_mat);
3775 writeq(rx_mat, &bar0->rx_mat);
3776 readq(&bar0->rx_mat);
3820 struct XENA_dev_config __iomem *bar0 = sp->bar0;
3835 saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3839 writeq(val64, &bar0->scheduled_int_ctrl);
3854 writeq(saved64, &bar0->scheduled_int_ctrl);
4204 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4213 addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4232 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4239 reason = readq(&bar0->general_int_status);
4245 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4251 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4256 writeq(sp->general_int_mask, &bar0->general_int_mask);
4257 readl(&bar0->general_int_status);
4266 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4269 val64 = readq(&bar0->pic_int_status);
4271 val64 = readq(&bar0->gpio_int_reg);
4280 writeq(val64, &bar0->gpio_int_reg);
4281 val64 = readq(&bar0->gpio_int_mask);
4284 writeq(val64, &bar0->gpio_int_mask);
4286 val64 = readq(&bar0->adapter_status);
4288 val64 = readq(&bar0->adapter_control);
4290 writeq(val64, &bar0->adapter_control);
4292 writeq(val64, &bar0->adapter_control);
4301 val64 = readq(&bar0->gpio_int_mask);
4304 writeq(val64, &bar0->gpio_int_mask);
4307 val64 = readq(&bar0->adapter_status);
4310 val64 = readq(&bar0->gpio_int_mask);
4313 writeq(val64, &bar0->gpio_int_mask);
4316 val64 = readq(&bar0->adapter_control);
4318 writeq(val64, &bar0->adapter_control);
4321 val64 = readq(&bar0->gpio_int_mask);
4360 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4388 val64 = readq(&bar0->mac_rmac_err_reg);
4389 writeq(val64, &bar0->mac_rmac_err_reg);
4395 if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4400 if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4406 val64 = readq(&bar0->ring_bump_counter1);
4413 val64 = readq(&bar0->ring_bump_counter2);
4421 val64 = readq(&bar0->txdma_int_status);
4427 &bar0->pfc_err_reg,
4431 &bar0->pfc_err_reg,
4440 &bar0->tda_err_reg,
4444 &bar0->tda_err_reg,
4454 &bar0->pcc_err_reg,
4458 &bar0->pcc_err_reg,
4465 &bar0->tti_err_reg,
4469 &bar0->tti_err_reg,
4477 &bar0->lso_err_reg,
4481 &bar0->lso_err_reg,
4488 &bar0->tpa_err_reg,
4492 &bar0->tpa_err_reg,
4499 &bar0->sm_err_reg,
4504 val64 = readq(&bar0->mac_int_status);
4507 &bar0->mac_tmac_err_reg,
4513 &bar0->mac_tmac_err_reg,
4517 val64 = readq(&bar0->xgxs_int_status);
4520 &bar0->xgxs_txgxs_err_reg,
4524 &bar0->xgxs_txgxs_err_reg,
4528 val64 = readq(&bar0->rxdma_int_status);
4534 &bar0->rc_err_reg,
4539 RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4544 &bar0->prc_pcix_err_reg,
4550 &bar0->prc_pcix_err_reg,
4556 &bar0->rpa_err_reg,
4560 &bar0->rpa_err_reg,
4570 &bar0->rda_err_reg,
4577 &bar0->rda_err_reg,
4583 &bar0->rti_err_reg,
4587 &bar0->rti_err_reg,
4591 val64 = readq(&bar0->mac_int_status);
4594 &bar0->mac_rmac_err_reg,
4600 &bar0->mac_rmac_err_reg,
4604 val64 = readq(&bar0->xgxs_int_status);
4607 &bar0->xgxs_rxgxs_err_reg,
4612 val64 = readq(&bar0->mc_int_status);
4615 &bar0->mc_err_reg,
4621 writeq(val64, &bar0->mc_err_reg);
4662 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4685 reason = readq(&bar0->general_int_status);
4692 writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4697 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4698 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4699 readl(&bar0->rx_traffic_int);
4708 writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4723 writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4741 writeq(sp->general_int_mask, &bar0->general_int_mask);
4742 readl(&bar0->general_int_status);
4759 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4767 writeq(val64, &bar0->stat_cfg);
4770 val64 = readq(&bar0->stat_cfg);
4886 struct XENA_dev_config __iomem *bar0 = sp->bar0;
4896 &bar0->rmac_addr_data0_mem);
4898 &bar0->rmac_addr_data1_mem);
4902 writeq(val64, &bar0->rmac_addr_cmd_mem);
4904 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4913 &bar0->rmac_addr_data0_mem);
4915 &bar0->rmac_addr_data1_mem);
4919 writeq(val64, &bar0->rmac_addr_cmd_mem);
4921 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4931 add = &bar0->mac_cfg;
4932 val64 = readq(&bar0->mac_cfg);
4935 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4937 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4941 val64 = readq(&bar0->rx_pa_cfg);
4943 writeq(val64, &bar0->rx_pa_cfg);
4947 val64 = readq(&bar0->mac_cfg);
4953 add = &bar0->mac_cfg;
4954 val64 = readq(&bar0->mac_cfg);
4957 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4959 writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4963 val64 = readq(&bar0->rx_pa_cfg);
4965 writeq(val64, &bar0->rx_pa_cfg);
4969 val64 = readq(&bar0->mac_cfg);
4991 &bar0->rmac_addr_data0_mem);
4993 &bar0->rmac_addr_data1_mem);
4998 writeq(val64, &bar0->rmac_addr_cmd_mem);
5001 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5021 &bar0->rmac_addr_data0_mem);
5023 &bar0->rmac_addr_data1_mem);
5028 writeq(val64, &bar0->rmac_addr_cmd_mem);
5031 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5118 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5121 &bar0->rmac_addr_data0_mem);
5125 writeq(val64, &bar0->rmac_addr_cmd_mem);
5128 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5164 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5169 writeq(val64, &bar0->rmac_addr_cmd_mem);
5172 if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5178 tmp64 = readq(&bar0->rmac_addr_data0_mem);
5370 reg = readq(sp->bar0 + i);
5380 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5386 val64 = readq(&bar0->gpio_control);
5392 writeq(val64, &bar0->gpio_control);
5394 val64 = readq(&bar0->adapter_control);
5400 writeq(val64, &bar0->adapter_control);
5421 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5425 u64 val64 = readq(&bar0->adapter_control);
5434 sp->adapt_ctrl_org = readq(&bar0->gpio_control);
5447 writeq(sp->adapt_ctrl_org, &bar0->gpio_control);
5494 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5496 val64 = readq(&bar0->rmac_pause_cfg);
5520 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5522 val64 = readq(&bar0->rmac_pause_cfg);
5531 writeq(val64, &bar0->rmac_pause_cfg);
5556 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5564 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5567 val64 = readq(&bar0->i2c_control);
5582 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5584 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5586 val64 = readq(&bar0->spi_control);
5591 *data = readq(&bar0->spi_data);
5622 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5630 SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5633 val64 = readq(&bar0->i2c_control);
5646 writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
5651 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5653 SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5655 val64 = readq(&bar0->spi_control);
5841 struct XENA_dev_config __iomem *bar0 = sp->bar0;
5845 val64 = readq(&bar0->pif_rd_swapper_fb);
5851 val64 = readq(&bar0->rmac_pause_cfg);
5857 val64 = readq(&bar0->rx_queue_cfg);
5867 val64 = readq(&bar0->xgxs_efifo_cfg);
5874 writeq(val64, &bar0->xmsi_data);
5875 val64 = readq(&bar0->xmsi_data);
5882 writeq(val64, &bar0->xmsi_data);
5883 val64 = readq(&bar0->xmsi_data);
6046 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6049 val64 = readq(&bar0->adapter_status);
6073 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6077 val64 = readq(&bar0->adapter_control);
6079 writeq(val64, &bar0->adapter_control);
6081 val64 = readq(&bar0->mc_rldram_test_ctrl);
6083 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6085 val64 = readq(&bar0->mc_rldram_mrs);
6087 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6090 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6096 writeq(val64, &bar0->mc_rldram_test_d0);
6101 writeq(val64, &bar0->mc_rldram_test_d1);
6106 writeq(val64, &bar0->mc_rldram_test_d2);
6109 writeq(val64, &bar0->mc_rldram_test_add);
6114 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6117 val64 = readq(&bar0->mc_rldram_test_ctrl);
6127 SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6130 val64 = readq(&bar0->mc_rldram_test_ctrl);
6139 val64 = readq(&bar0->mc_rldram_test_ctrl);
6149 SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6644 struct XENA_dev_config __iomem *bar0 = sp->bar0;
6647 writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6664 struct XENA_dev_config __iomem *bar0 = nic->bar0;
6687 val64 = readq(&bar0->adapter_status);
6689 if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6691 val64 = readq(&bar0->adapter_control);
6693 writeq(val64, &bar0->adapter_control);
6696 val64 = readq(&bar0->gpio_control);
6698 writeq(val64, &bar0->gpio_control);
6699 val64 = readq(&bar0->gpio_control);
6702 writeq(val64, &bar0->adapter_control);
6712 val64 = readq(&bar0->adapter_control);
6714 writeq(val64, &bar0->adapter_control);
6719 val64 = readq(&bar0->gpio_control);
6721 writeq(val64, &bar0->gpio_control);
6722 val64 = readq(&bar0->gpio_control);
6725 val64 = readq(&bar0->adapter_control);
6727 writeq(val64, &bar0->adapter_control);
7006 struct XENA_dev_config __iomem *bar0 = sp->bar0;
7051 val64 = readq(&bar0->adapter_status);
7601 struct XENA_dev_config __iomem *bar0 = nic->bar0;
7608 writeq(val64, &bar0->rts_ds_mem_data);
7614 writeq(val64, &bar0->rts_ds_mem_ctrl);
7616 return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7661 struct XENA_dev_config __iomem *bar0 = NULL;
7840 sp->bar0 = pci_ioremap_bar(pdev, 0);
7841 if (!sp->bar0) {
7937 bar0 = sp->bar0;
7940 writeq(val64, &bar0->rmac_addr_cmd_mem);
7941 wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7944 tmp64 = readq(&bar0->rmac_addr_data0_mem);
8006 val64 = readq(&bar0->gpio_control);
8008 writeq(val64, &bar0->gpio_control);
8010 writeq(val64, (void __iomem *)bar0 + 0x2700);
8011 val64 = readq(&bar0->gpio_control);
8123 iounmap(sp->bar0);
8161 iounmap(sp->bar0);