Lines Matching defs:config
500 if (!sp->config.multiq) {
503 for (i = 0; i < sp->config.tx_fifo_num; i++)
511 if (!sp->config.multiq)
520 if (!sp->config.multiq) {
523 for (i = 0; i < sp->config.tx_fifo_num; i++)
531 if (!sp->config.multiq) {
534 for (i = 0; i < sp->config.tx_fifo_num; i++)
574 struct config_param *config = &nic->config;
580 for (i = 0; i < config->tx_fifo_num; i++) {
581 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
593 for (i = 0; i < config->tx_fifo_num; i++) {
594 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
608 lst_size = (sizeof(struct TxD) * config->max_txds);
611 for (i = 0; i < config->tx_fifo_num; i++) {
613 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
624 for (i = 0; i < config->tx_fifo_num; i++) {
625 int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
628 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
684 for (i = 0; i < config->tx_fifo_num; i++) {
686 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
697 for (i = 0; i < config->rx_ring_num; i++) {
698 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
717 for (i = 0; i < config->rx_ring_num; i++) {
718 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
789 for (i = 0; i < config->rx_ring_num; i++) {
790 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
877 struct config_param *config;
887 config = &nic->config;
892 lst_size = sizeof(struct TxD) * config->max_txds;
895 for (i = 0; i < config->tx_fifo_num; i++) {
897 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
934 for (i = 0; i < config->rx_ring_num; i++) {
954 for (i = 0; i < config->rx_ring_num; i++) {
955 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
984 for (i = 0; i < nic->config.tx_fifo_num; i++) {
986 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1046 struct config_param *config = &nic->config;
1055 config->bus_speed = bus_speed[mode];
1114 struct config_param *config = &nic->config;
1116 for (i = 0; i < config->tx_fifo_num; i++) {
1123 int count = (nic->config.bus_speed * 125)/2;
1137 if (nic->config.intr_type == MSI_X) {
1143 if ((nic->config.tx_steering_type ==
1145 (config->tx_fifo_num > 1) &&
1196 struct config_param *config = &nic->config;
1277 for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1278 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1283 if (i == (config->tx_fifo_num - 1)) {
1339 for (i = 0; i < config->rx_ring_num; i++) {
1340 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1356 for (i = 0; i < config->rx_ring_num; i++) {
1359 mem_share = (mem_size / config->rx_ring_num +
1360 mem_size % config->rx_ring_num);
1364 mem_share = (mem_size / config->rx_ring_num);
1368 mem_share = (mem_size / config->rx_ring_num);
1372 mem_share = (mem_size / config->rx_ring_num);
1376 mem_share = (mem_size / config->rx_ring_num);
1380 mem_share = (mem_size / config->rx_ring_num);
1384 mem_share = (mem_size / config->rx_ring_num);
1388 mem_share = (mem_size / config->rx_ring_num);
1399 switch (config->tx_fifo_num) {
1494 switch (config->rx_ring_num) {
1611 for (i = 0 ; i < config->rx_ring_num ; i++)
1617 for (i = 0; i < config->rx_ring_num; i++) {
1671 int count = (nic->config.bus_speed * 125)/4;
1684 if (nic->config.intr_type == MSI_X)
1692 for (i = 0; i < config->rx_ring_num; i++) {
1790 if (nic->config.bus_speed == 266) {
2213 struct config_param *config = &nic->config;
2217 for (i = 0; i < config->rx_ring_num; i++) {
2371 struct config_param *config = &nic->config;
2376 for (i = 0; i < config->tx_fifo_num; i++) {
2377 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2717 struct config_param *config = &sp->config;
2720 for (i = 0; i < config->rx_ring_num; i++) {
2794 struct config_param *config = &nic->config;
2800 for (i = 0; i < config->rx_ring_num; i++) {
2835 struct config_param *config = &nic->config;
2850 for (i = 0; i < config->tx_fifo_num; i++)
2854 for (i = 0; i < config->rx_ring_num; i++) {
2860 for (i = 0; i < config->rx_ring_num; i++) {
2958 if (ring_data->nic->config.napi) {
3068 s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3605 if (sp->config.intr_type == INTA)
3629 if (sp->config.intr_type == INTA)
3768 for (j = 0; j < nic->config.rx_ring_num; j++) {
3936 if (sp->config.intr_type == MSI_X) {
3967 struct config_param *config = &sp->config;
3979 for (offset = 1; offset < config->max_mc_addr; offset++) {
4015 struct config_param *config = &sp->config;
4038 if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4068 } else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4070 queue = config->fifo_mapping
4076 if (sp->config.multiq) {
4176 if (sp->config.intr_type == MSI_X)
4209 if (sp->config.napi) {
4233 struct config_param *config = &sp->config;
4253 for (i = 0; i < config->tx_fifo_num; i++)
4666 struct config_param *config;
4675 config = &sp->config;
4694 if (config->napi) {
4710 for (i = 0; i < config->rx_ring_num; i++) {
4725 for (i = 0; i < config->tx_fifo_num; i++)
4734 if (!config->napi) {
4735 for (i = 0; i < config->rx_ring_num; i++) {
4891 struct config_param *config = &sp->config;
4901 RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4909 sp->all_multi_pos = config->max_mc_addr - 1;
4977 (config->max_mc_addr - config->max_mac_addr)) {
4997 (config->mc_start_offset + i);
5027 (i + config->mc_start_offset);
5051 struct config_param *config = &sp->config;
5054 for (offset = 0; offset < config->max_mc_addr; offset++) {
5067 struct config_param *config = &sp->config;
5069 for (offset = 0; offset < config->max_mac_addr; offset++)
5074 for (offset = config->mc_start_offset;
5075 offset < config->max_mc_addr; offset++)
5084 struct config_param *config = &sp->config;
5094 for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5103 if (i == config->max_mc_addr) {
5141 struct config_param *config = &sp->config;
5144 offset < config->max_mc_addr; offset++) {
5215 struct config_param *config = &sp->config;
5234 for (i = 1; i < config->max_mac_addr; i++) {
5246 if (i == config->max_mac_addr) {
5469 for (i = 0; i < sp->config.rx_ring_num; i++)
5470 rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5474 for (i = 0; i < sp->config.tx_fifo_num; i++)
5475 tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5477 DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
6853 struct config_param *config = &sp->config;
6869 for (i = 0; i < config->rx_ring_num; i++) {
6870 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
6905 if (sp->config.intr_type == MSI_X)
6909 sp->config.intr_type = INTA;
6919 if (sp->config.intr_type == MSI_X) {
6970 sp->config.intr_type = INTA;
6983 if (sp->config.intr_type == INTA) {
6997 if (sp->config.intr_type == MSI_X)
7008 struct config_param *config;
7009 config = &sp->config;
7021 if (sp->config.napi) {
7023 if (config->intr_type == MSI_X) {
7024 for (; off < sp->config.rx_ring_num; off++)
7086 struct config_param *config;
7105 config = &sp->config;
7108 for (i = 0; i < config->rx_ring_num; i++) {
7125 if (config->napi) {
7126 if (config->intr_type == MSI_X) {
7127 for (i = 0; i < sp->config.rx_ring_num; i++)
7162 if (sp->config.intr_type == MSI_X)
7175 if (sp->config.intr_type != INTA) {
7187 if (config->napi) {
7188 if (config->intr_type == MSI_X) {
7189 for (i = 0; i < sp->config.rx_ring_num; i++)
7663 struct config_param *config;
7727 sp->config.intr_type = dev_intr_type;
7746 config = &sp->config;
7749 config->napi = napi;
7750 config->tx_steering_type = tx_steering_type;
7753 if (config->tx_steering_type == TX_PRIORITY_STEERING)
7754 config->tx_fifo_num = MAX_TX_FIFOS;
7756 config->tx_fifo_num = tx_fifo_num;
7759 if (config->tx_fifo_num < 5) {
7760 if (config->tx_fifo_num == 1)
7763 sp->total_tcp_fifos = config->tx_fifo_num - 1;
7764 sp->udp_fifo_idx = config->tx_fifo_num - 1;
7775 config->multiq = dev_multiq;
7776 for (i = 0; i < config->tx_fifo_num; i++) {
7777 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7785 config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7788 for (i = 0; i < config->tx_fifo_num; i++)
7792 config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7793 for (i = 0; i < config->tx_fifo_num; i++) {
7794 struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7798 config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7803 config->max_txds = MAX_SKB_FRAGS + 2;
7806 config->rx_ring_num = rx_ring_num;
7807 for (i = 0; i < config->rx_ring_num; i++) {
7808 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7821 struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7896 if (sp->config.intr_type == MSI_X) {
7897 sp->num_entries = config->rx_ring_num + 1;
7909 sp->config.intr_type = INTA;
7913 if (config->intr_type == MSI_X) {
7914 for (i = 0; i < config->rx_ring_num ; i++) {
7961 config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
7962 config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
7963 config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
7965 config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
7966 config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
7967 config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
7979 (config->intr_type == MSI_X))
7980 sp->num_entries = config->rx_ring_num + 1;
7994 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8048 switch (sp->config.napi) {
8058 sp->config.tx_fifo_num);
8061 sp->config.rx_ring_num);
8063 switch (sp->config.intr_type) {
8071 if (sp->config.multiq) {
8072 for (i = 0; i < sp->config.tx_fifo_num; i++) {
8075 fifo->multiq = config->multiq;
8083 switch (sp->config.tx_steering_type) {
8474 if (sp->config.napi)
8532 * followed by fixups by BIOS, and has its config space