Lines Matching defs:mgp
179 struct myri10ge_priv *mgp;
368 static void set_fw_name(struct myri10ge_priv *mgp, char *name, bool allocated)
370 if (mgp->fw_name_allocated)
371 kfree(mgp->fw_name);
372 mgp->fw_name = name;
373 mgp->fw_name_allocated = allocated;
377 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
382 struct mcp_cmd_response *response = mgp->cmd;
383 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
394 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
395 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
445 dev_err(&mgp->pdev->dev,
452 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
464 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
469 ptr = mgp->eeprom_strings;
470 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
475 mgp->mac_addr_string = ptr;
479 mgp->mac_addr[i] =
486 mgp->product_code_string = ptr;
490 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
498 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
507 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
515 mgp->cmd->data = 0;
522 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
523 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
532 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
535 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
537 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
538 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
543 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
546 struct device *dev = &mgp->pdev->dev;
555 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
556 mgp->fw_version[sizeof(mgp->fw_version) - 1] = '\0';
558 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
559 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
561 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR &&
562 mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
563 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
571 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
575 struct device *dev = &mgp->pdev->dev;
582 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
584 mgp->fw_name);
591 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
607 status = myri10ge_validate_firmware(mgp, hdr);
613 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
617 readb(mgp->sram);
625 memcpy_fromio(fw_readback, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
643 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
646 struct device *dev = &mgp->pdev->dev;
652 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
654 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
666 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
667 status = myri10ge_validate_firmware(mgp, hdr);
673 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
674 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
675 mgp->adopted_rx_filter_bug = 1;
678 mgp->fw_ver_major, mgp->fw_ver_minor,
679 mgp->fw_ver_tiny);
684 static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
690 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
691 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
694 mgp->max_tso6 = cmd.data0;
695 mgp->features |= NETIF_F_TSO6;
698 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
700 dev_err(&mgp->pdev->dev,
705 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
710 static int myri10ge_load_firmware(struct myri10ge_priv *mgp, int adopt)
718 status = myri10ge_load_hotplug_firmware(mgp, &size);
722 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
729 status = myri10ge_adopt_running_firmware(mgp);
731 dev_err(&mgp->pdev->dev,
735 dev_info(&mgp->pdev->dev,
737 if (mgp->tx_boundary == 4096) {
738 dev_warn(&mgp->pdev->dev,
741 dev_warn(&mgp->pdev->dev,
744 dev_warn(&mgp->pdev->dev, "via hotplug\n");
747 set_fw_name(mgp, "adopted", false);
748 mgp->tx_boundary = 2048;
749 myri10ge_dummy_rdma(mgp, 1);
750 status = myri10ge_get_firmware_capabilities(mgp);
755 mgp->cmd->data = 0;
762 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
763 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
778 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
785 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
789 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
790 dev_err(&mgp->pdev->dev, "handoff failed\n");
793 myri10ge_dummy_rdma(mgp, 1);
794 status = myri10ge_get_firmware_capabilities(mgp);
799 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
809 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
813 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
819 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
822 netdev_err(mgp->dev, "Failed to set flow control mode\n");
825 mgp->pause = pause;
830 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
836 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
838 netdev_err(mgp->dev, "Failed to set promisc mode\n");
841 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
853 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
855 if (unlikely(pci_dma_mapping_error(mgp->pdev, dmatest_bus))) {
869 len = mgp->tx_boundary;
874 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
879 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
883 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
888 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
893 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
898 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
902 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
906 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
912 static int myri10ge_reset(struct myri10ge_priv *mgp)
925 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
927 dev_err(&mgp->pdev->dev, "failed reset\n");
931 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
939 (void)myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE, &cmd, 0);
943 bytes = mgp->max_intr_slots * sizeof(*mgp->ss[0].rx_done.entry);
945 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
958 if (mgp->num_slices > 1) {
961 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES,
964 dev_err(&mgp->pdev->dev,
973 cmd.data0 = mgp->num_slices;
975 if (mgp->dev->real_num_tx_queues > 1)
977 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
983 if (status != 0 && mgp->dev->real_num_tx_queues > 1) {
984 netif_set_real_num_tx_queues(mgp->dev, 1);
985 cmd.data0 = mgp->num_slices;
987 status = myri10ge_send_cmd(mgp,
993 dev_err(&mgp->pdev->dev,
999 for (i = 0; i < mgp->num_slices; i++) {
1000 ss = &mgp->ss[i];
1004 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA,
1009 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
1010 for (i = 0; i < mgp->num_slices; i++) {
1011 ss = &mgp->ss[i];
1013 (__iomem __be32 *) (mgp->sram + cmd.data0 + 8 * i);
1015 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
1017 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
1020 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
1021 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
1023 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
1026 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1029 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_DCA_OFFSET, &cmd, 0);
1031 for (i = 0; i < mgp->num_slices; i++) {
1032 ss = &mgp->ss[i];
1035 (mgp->sram + dca_tag_off + 4 * i);
1044 mgp->link_changes = 0;
1045 for (i = 0; i < mgp->num_slices; i++) {
1046 ss = &mgp->ss[i];
1061 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
1062 myri10ge_change_pause(mgp, mgp->pause);
1063 myri10ge_set_multicast_list(mgp->dev);
1097 tag = dca3_get_tag(&ss->mgp->pdev->dev, cpu);
1105 static void myri10ge_setup_dca(struct myri10ge_priv *mgp)
1108 struct pci_dev *pdev = mgp->pdev;
1110 if (mgp->ss[0].dca_tag == NULL || mgp->dca_enabled)
1123 mgp->relaxed_order = myri10ge_toggle_relaxed(pdev, 0);
1124 mgp->dca_enabled = 1;
1125 for (i = 0; i < mgp->num_slices; i++) {
1126 mgp->ss[i].cpu = -1;
1127 mgp->ss[i].cached_dca_tag = -1;
1128 myri10ge_update_dca(&mgp->ss[i]);
1132 static void myri10ge_teardown_dca(struct myri10ge_priv *mgp)
1134 struct pci_dev *pdev = mgp->pdev;
1136 if (!mgp->dca_enabled)
1138 mgp->dca_enabled = 0;
1139 if (mgp->relaxed_order)
1146 struct myri10ge_priv *mgp;
1149 mgp = dev_get_drvdata(dev);
1153 myri10ge_setup_dca(mgp);
1155 myri10ge_teardown_dca(mgp);
1178 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
1208 bus = pci_map_page(mgp->pdev, page, 0,
1211 if (unlikely(pci_dma_mapping_error(mgp->pdev, bus))) {
1307 struct myri10ge_priv *mgp = ss->mgp;
1312 struct pci_dev *pdev = mgp->pdev;
1313 struct net_device *dev = mgp->dev;
1316 if (len <= mgp->small_bytes) {
1318 bytes = mgp->small_bytes;
1321 bytes = mgp->big_bytes;
1366 myri10ge_vlan_rx(mgp->dev, va, skb);
1367 skb_record_rx_queue(skb, ss - &mgp->ss[0]);
1377 struct pci_dev *pdev = ss->mgp->pdev;
1414 dev_queue = netdev_get_tx_queue(ss->dev, ss - ss->mgp->ss);
1424 if ((ss->mgp->dev->real_num_tx_queues > 1) &&
1437 ss->mgp->running == MYRI10GE_ETH_RUNNING) {
1447 struct myri10ge_priv *mgp = ss->mgp;
1465 idx = cnt & (mgp->max_intr_slots - 1);
1475 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1476 mgp->small_bytes + MXGEFW_PAD, 0);
1478 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1483 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1485 struct mcp_irq_data *stats = mgp->ss[0].fw_stats;
1489 if (mgp->link_state != link_up) {
1490 mgp->link_state = link_up;
1492 if (mgp->link_state == MXGEFW_LINK_UP) {
1493 netif_info(mgp, link, mgp->dev, "link up\n");
1494 netif_carrier_on(mgp->dev);
1495 mgp->link_changes++;
1497 netif_info(mgp, link, mgp->dev, "link %s\n",
1501 netif_carrier_off(mgp->dev);
1502 mgp->link_changes++;
1505 if (mgp->rdma_tags_available !=
1507 mgp->rdma_tags_available =
1509 netdev_warn(mgp->dev, "RDMA timed out! %d tags left\n",
1510 mgp->rdma_tags_available);
1512 mgp->down_cnt += stats->link_down;
1514 wake_up(&mgp->down_wq);
1525 if (ss->mgp->dca_enabled)
1541 struct myri10ge_priv *mgp = ss->mgp;
1549 if ((mgp->dev->real_num_tx_queues == 1) && (ss != mgp->ss)) {
1563 if (!mgp->msi_enabled && !mgp->msix_enabled) {
1564 put_be32(0, mgp->irq_deassert);
1580 netdev_warn(mgp->dev, "irq stuck?\n");
1582 schedule_work(&mgp->watchdog_work);
1591 if (ss == mgp->ss)
1592 myri10ge_check_statblock(mgp);
1602 struct myri10ge_priv *mgp = netdev_priv(netdev);
1616 ptr = mgp->product_code_string;
1625 mgp->product_code_string);
1646 struct myri10ge_priv *mgp = netdev_priv(netdev);
1650 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1651 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1657 struct myri10ge_priv *mgp = netdev_priv(netdev);
1659 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1666 struct myri10ge_priv *mgp = netdev_priv(netdev);
1668 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1669 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1677 struct myri10ge_priv *mgp = netdev_priv(netdev);
1680 pause->rx_pause = mgp->pause;
1681 pause->tx_pause = mgp->pause;
1688 struct myri10ge_priv *mgp = netdev_priv(netdev);
1690 if (pause->tx_pause != mgp->pause)
1691 return myri10ge_change_pause(mgp, pause->tx_pause);
1692 if (pause->rx_pause != mgp->pause)
1693 return myri10ge_change_pause(mgp, pause->rx_pause);
1703 struct myri10ge_priv *mgp = netdev_priv(netdev);
1705 ring->rx_mini_max_pending = mgp->ss[0].rx_small.mask + 1;
1706 ring->rx_max_pending = mgp->ss[0].rx_big.mask + 1;
1708 ring->tx_max_pending = mgp->ss[0].tx.mask + 1;
1751 struct myri10ge_priv *mgp = netdev_priv(netdev);
1759 for (i = 0; i < mgp->num_slices; i++) {
1770 struct myri10ge_priv *mgp = netdev_priv(netdev);
1775 mgp->num_slices * MYRI10GE_SLICE_STATS_LEN;
1785 struct myri10ge_priv *mgp = netdev_priv(netdev);
1797 data[i++] = (unsigned int)mgp->tx_boundary;
1798 data[i++] = (unsigned int)mgp->pdev->irq;
1799 data[i++] = (unsigned int)mgp->msi_enabled;
1800 data[i++] = (unsigned int)mgp->msix_enabled;
1801 data[i++] = (unsigned int)mgp->read_dma;
1802 data[i++] = (unsigned int)mgp->write_dma;
1803 data[i++] = (unsigned int)mgp->read_write_dma;
1804 data[i++] = (unsigned int)mgp->serial_number;
1805 data[i++] = (unsigned int)mgp->watchdog_resets;
1807 data[i++] = (unsigned int)(mgp->ss[0].dca_tag != NULL);
1808 data[i++] = (unsigned int)(mgp->dca_enabled);
1810 data[i++] = (unsigned int)mgp->link_changes;
1813 ss = &mgp->ss[0];
1829 for (slice = 0; slice < mgp->num_slices; slice++) {
1830 ss = &mgp->ss[slice];
1846 struct myri10ge_priv *mgp = netdev_priv(netdev);
1847 mgp->msg_enable = value;
1852 struct myri10ge_priv *mgp = netdev_priv(netdev);
1853 return mgp->msg_enable;
1861 static int myri10ge_led(struct myri10ge_priv *mgp, int on)
1864 struct device *dev = &mgp->pdev->dev;
1869 hdr_off = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
1870 if ((hdr_off & 3) || hdr_off + sizeof(*hdr) > mgp->sram_size) {
1875 hdr_len = swab32(readl(mgp->sram + hdr_off +
1883 pattern = swab32(readl(mgp->sram + pattern_off + 4));
1884 writel(swab32(pattern), mgp->sram + pattern_off);
1891 struct myri10ge_priv *mgp = netdev_priv(netdev);
1896 rc = myri10ge_led(mgp, 1);
1900 rc = myri10ge_led(mgp, 0);
1930 struct myri10ge_priv *mgp = ss->mgp;
1932 struct net_device *dev = mgp->dev;
1939 slice = ss - mgp->ss;
1941 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1944 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
2005 if (mgp->small_bytes == 0) {
2008 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
2009 mgp->small_bytes + MXGEFW_PAD, 0);
2018 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
2030 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2031 mgp->big_bytes);
2036 if (mgp->small_bytes == 0)
2040 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2041 mgp->small_bytes + MXGEFW_PAD);
2070 struct myri10ge_priv *mgp = ss->mgp;
2083 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
2084 mgp->big_bytes);
2088 if (mgp->small_bytes == 0)
2095 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
2096 mgp->small_bytes + MXGEFW_PAD);
2113 pci_unmap_single(mgp->pdev,
2119 pci_unmap_page(mgp->pdev,
2140 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
2142 struct pci_dev *pdev = mgp->pdev;
2144 struct net_device *netdev = mgp->dev;
2148 mgp->msi_enabled = 0;
2149 mgp->msix_enabled = 0;
2152 if (mgp->num_slices > 1) {
2153 status = pci_enable_msix_range(pdev, mgp->msix_vectors,
2154 mgp->num_slices, mgp->num_slices);
2160 mgp->msix_enabled = 1;
2162 if (mgp->msix_enabled == 0) {
2169 mgp->msi_enabled = 1;
2173 if (mgp->msix_enabled) {
2174 for (i = 0; i < mgp->num_slices; i++) {
2175 ss = &mgp->ss[i];
2178 status = request_irq(mgp->msix_vectors[i].vector,
2186 free_irq(mgp->msix_vectors[i].vector,
2187 &mgp->ss[i]);
2196 mgp->dev->name, &mgp->ss[0]);
2199 if (mgp->msi_enabled)
2206 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
2208 struct pci_dev *pdev = mgp->pdev;
2211 if (mgp->msix_enabled) {
2212 for (i = 0; i < mgp->num_slices; i++)
2213 free_irq(mgp->msix_vectors[i].vector, &mgp->ss[i]);
2215 free_irq(pdev->irq, &mgp->ss[0]);
2217 if (mgp->msi_enabled)
2219 if (mgp->msix_enabled)
2223 static int myri10ge_get_txrx(struct myri10ge_priv *mgp, int slice)
2229 ss = &mgp->ss[slice];
2231 if (slice == 0 || (mgp->dev->real_num_tx_queues > 1)) {
2233 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET,
2236 (mgp->sram + cmd.data0);
2239 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET,
2242 (mgp->sram + cmd.data0);
2245 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
2247 (mgp->sram + cmd.data0);
2250 (mgp->sram + MXGEFW_ETH_SEND_GO + 64 * slice);
2252 (mgp->sram + MXGEFW_ETH_SEND_STOP + 64 * slice);
2257 static int myri10ge_set_stats(struct myri10ge_priv *mgp, int slice)
2263 ss = &mgp->ss[slice];
2267 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2275 status = myri10ge_send_cmd(mgp,
2279 mgp->fw_multicast_support = 0;
2281 mgp->fw_multicast_support = 1;
2289 struct myri10ge_priv *mgp = netdev_priv(dev);
2294 if (mgp->running != MYRI10GE_ETH_STOPPED)
2297 mgp->running = MYRI10GE_ETH_STARTING;
2298 status = myri10ge_reset(mgp);
2304 if (mgp->num_slices > 1) {
2305 cmd.data0 = mgp->num_slices;
2307 if (mgp->dev->real_num_tx_queues > 1)
2309 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ENABLE_RSS_QUEUES,
2316 cmd.data0 = mgp->num_slices;
2317 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_TABLE_SIZE,
2320 status |= myri10ge_send_cmd(mgp,
2329 itable = mgp->sram + cmd.data0;
2330 for (i = 0; i < mgp->num_slices; i++)
2335 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_RSS_ENABLE,
2343 status = myri10ge_request_irq(mgp);
2355 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
2360 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
2364 mgp->small_bytes = myri10ge_small_bytes;
2374 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2377 mgp->big_bytes = big_pow2;
2381 for (slice = 0; slice < mgp->num_slices; slice++) {
2382 ss = &mgp->ss[slice];
2384 status = myri10ge_get_txrx(mgp, slice);
2396 if (slice == 0 || mgp->dev->real_num_tx_queues > 1)
2397 status = myri10ge_set_stats(mgp, slice);
2409 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2410 cmd.data0 = mgp->small_bytes;
2412 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2415 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2427 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_TSO_MODE, &cmd, 0);
2433 mgp->link_state = ~0U;
2434 mgp->rdma_tags_available = 15;
2436 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2442 mgp->running = MYRI10GE_ETH_RUNNING;
2443 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2444 add_timer(&mgp->watchdog_timer);
2452 napi_disable(&mgp->ss[slice].napi);
2454 for (i = 0; i < mgp->num_slices; i++)
2455 myri10ge_free_rings(&mgp->ss[i]);
2457 myri10ge_free_irq(mgp);
2460 mgp->running = MYRI10GE_ETH_STOPPED;
2466 struct myri10ge_priv *mgp = netdev_priv(dev);
2471 if (mgp->running != MYRI10GE_ETH_RUNNING)
2474 if (mgp->ss[0].tx.req_bytes == NULL)
2477 del_timer_sync(&mgp->watchdog_timer);
2478 mgp->running = MYRI10GE_ETH_STOPPING;
2479 for (i = 0; i < mgp->num_slices; i++)
2480 napi_disable(&mgp->ss[i].napi);
2485 if (mgp->rebooted == 0) {
2486 old_down_cnt = mgp->down_cnt;
2489 myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2493 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt,
2495 if (old_down_cnt == mgp->down_cnt)
2499 myri10ge_free_irq(mgp);
2500 for (i = 0; i < mgp->num_slices; i++)
2501 myri10ge_free_rings(&mgp->ss[i]);
2503 mgp->running = MYRI10GE_ETH_STOPPED;
2574 static void myri10ge_unmap_tx_dma(struct myri10ge_priv *mgp,
2587 pci_unmap_single(mgp->pdev,
2592 pci_unmap_page(mgp->pdev,
2616 struct myri10ge_priv *mgp = netdev_priv(dev);
2632 ss = &mgp->ss[queue];
2633 netdev_queue = netdev_get_tx_queue(mgp->dev, queue);
2695 if (unlikely(-cum_len > mgp->max_tso6))
2718 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2719 if (unlikely(pci_dma_mapping_error(mgp->pdev, bus)))
2752 * do not cross mgp->tx_boundary */
2763 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
2825 bus = skb_frag_dma_map(&mgp->pdev->dev, frag, 0, len,
2827 if (unlikely(pci_dma_mapping_error(mgp->pdev, bus))) {
2828 myri10ge_unmap_tx_dma(mgp, tx, idx);
2848 if ((mgp->dev->real_num_tx_queues > 1) && tx->queue_active == 0) {
2861 myri10ge_unmap_tx_dma(mgp, tx, idx);
2864 netdev_err(mgp->dev, "TSO but wanted to linearize?!?!?\n");
2885 struct myri10ge_priv *mgp = netdev_priv(dev);
2909 ss = &mgp->ss[skb_get_queue_mapping(skb)];
2918 const struct myri10ge_priv *mgp = netdev_priv(dev);
2922 for (i = 0; i < mgp->num_slices; i++) {
2923 slice_stats = &mgp->ss[i].stats;
2935 struct myri10ge_priv *mgp = netdev_priv(dev);
2943 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2946 if (!mgp->fw_multicast_support)
2951 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2958 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
2965 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2978 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2988 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
3004 struct myri10ge_priv *mgp = netdev_priv(dev);
3010 status = myri10ge_update_mac_address(mgp, sa->sa_data);
3024 struct myri10ge_priv *mgp = netdev_priv(dev);
3027 if (mgp->running) {
3045 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
3047 struct pci_dev *bridge = mgp->pdev->bus->self;
3048 struct device *dev = &mgp->pdev->dev;
3126 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
3128 struct pci_dev *pdev = mgp->pdev;
3132 mgp->tx_boundary = 4096;
3144 mgp->tx_boundary = 2048;
3150 set_fw_name(mgp, myri10ge_fw_aligned, false);
3151 status = myri10ge_load_firmware(mgp, 1);
3159 myri10ge_enable_ecrc(mgp);
3166 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
3177 mgp->tx_boundary = 2048;
3178 set_fw_name(mgp, myri10ge_fw_unaligned, false);
3181 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
3189 pcie_capability_read_word(mgp->pdev, PCI_EXP_LNKSTA, &lnk);
3196 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
3198 mgp->tx_boundary = 4096;
3199 set_fw_name(mgp, myri10ge_fw_aligned, false);
3201 myri10ge_firmware_probe(mgp);
3205 dev_info(&mgp->pdev->dev,
3207 mgp->tx_boundary = 4096;
3208 set_fw_name(mgp, myri10ge_fw_aligned, false);
3210 dev_info(&mgp->pdev->dev,
3212 mgp->tx_boundary = 2048;
3213 set_fw_name(mgp, myri10ge_fw_unaligned, false);
3222 set_fw_name(mgp, fw_name, true);
3227 if (mgp->board_number < MYRI10GE_MAX_BOARDS &&
3228 myri10ge_fw_names[mgp->board_number] != NULL &&
3229 strlen(myri10ge_fw_names[mgp->board_number])) {
3230 set_fw_name(mgp, myri10ge_fw_names[mgp->board_number], false);
3234 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
3235 mgp->fw_name);
3260 struct myri10ge_priv *mgp;
3263 mgp = dev_get_drvdata(dev);
3264 if (mgp == NULL)
3266 netdev = mgp->dev;
3275 myri10ge_dummy_rdma(mgp, 0);
3283 struct myri10ge_priv *mgp;
3288 mgp = pci_get_drvdata(pdev);
3289 if (mgp == NULL)
3291 netdev = mgp->dev;
3293 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3295 netdev_err(mgp->dev, "device disappeared!\n");
3299 myri10ge_reset(mgp);
3300 myri10ge_dummy_rdma(mgp, 1);
3318 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
3320 struct pci_dev *pdev = mgp->pdev;
3321 int vs = mgp->vendor_specific_offset;
3337 struct myri10ge_priv *mgp = ss->mgp;
3338 int slice = ss - mgp->ss;
3344 if (rx_pause_cnt != mgp->watchdog_pause) {
3346 netdev_warn(mgp->dev, "slice %d: TX paused, "
3349 netdev_warn(mgp->dev,
3354 (int)ntohl(mgp->ss[slice].fw_stats->
3375 struct myri10ge_priv *mgp =
3385 mgp->watchdog_resets++;
3386 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3392 reboot = myri10ge_read_reboot(mgp);
3393 netdev_err(mgp->dev, "NIC rebooted (0x%x),%s resetting\n",
3398 mgp->rebooted = 1;
3400 myri10ge_close(mgp->dev);
3402 mgp->rebooted = 0;
3410 pci_restore_state(mgp->pdev);
3413 pci_save_state(mgp->pdev);
3420 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3422 netdev_err(mgp->dev, "device disappeared!\n");
3428 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3429 for (i = 0; i < mgp->num_slices; i++) {
3430 ss = mgp->ss;
3439 netdev_dbg(mgp->dev, "not resetting\n");
3443 netdev_err(mgp->dev, "device timeout, resetting\n");
3448 myri10ge_close(mgp->dev);
3450 status = myri10ge_load_firmware(mgp, 1);
3452 netdev_err(mgp->dev, "failed to load firmware\n");
3454 myri10ge_open(mgp->dev);
3467 struct myri10ge_priv *mgp;
3473 mgp = from_timer(mgp, t, watchdog_timer);
3475 rx_pause_cnt = ntohl(mgp->ss[0].fw_stats->dropped_pause);
3478 i < mgp->num_slices && reset_needed == 0; ++i) {
3480 ss = &mgp->ss[i];
3482 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3483 mgp->small_bytes + MXGEFW_PAD,
3490 myri10ge_alloc_rx_pages(mgp, &ss->rx_big,
3491 mgp->big_bytes, 1);
3503 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
3508 mgp->watchdog_pause = rx_pause_cnt;
3511 schedule_work(&mgp->watchdog_work);
3514 mod_timer(&mgp->watchdog_timer,
3519 static void myri10ge_free_slices(struct myri10ge_priv *mgp)
3522 struct pci_dev *pdev = mgp->pdev;
3526 if (mgp->ss == NULL)
3529 for (i = 0; i < mgp->num_slices; i++) {
3530 ss = &mgp->ss[i];
3532 bytes = mgp->max_intr_slots *
3548 kfree(mgp->ss);
3549 mgp->ss = NULL;
3552 static int myri10ge_alloc_slices(struct myri10ge_priv *mgp)
3555 struct pci_dev *pdev = mgp->pdev;
3559 bytes = sizeof(*mgp->ss) * mgp->num_slices;
3560 mgp->ss = kzalloc(bytes, GFP_KERNEL);
3561 if (mgp->ss == NULL) {
3565 for (i = 0; i < mgp->num_slices; i++) {
3566 ss = &mgp->ss[i];
3567 bytes = mgp->max_intr_slots * sizeof(*ss->rx_done.entry);
3579 ss->mgp = mgp;
3580 ss->dev = mgp->dev;
3586 myri10ge_free_slices(mgp);
3596 static void myri10ge_probe_slices(struct myri10ge_priv *mgp)
3599 struct pci_dev *pdev = mgp->pdev;
3604 mgp->num_slices = 1;
3612 old_fw = mgp->fw_name;
3613 old_allocated = mgp->fw_name_allocated;
3615 mgp->fw_name_allocated = false;
3618 dev_info(&mgp->pdev->dev, "overriding rss firmware to %s\n",
3620 set_fw_name(mgp, myri10ge_fw_name, false);
3622 set_fw_name(mgp, myri10ge_fw_rss_aligned, false);
3624 set_fw_name(mgp, myri10ge_fw_rss_unaligned, false);
3625 status = myri10ge_load_firmware(mgp, 0);
3635 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
3637 dev_err(&mgp->pdev->dev, "failed reset\n");
3641 mgp->max_intr_slots = cmd.data0 / sizeof(struct mcp_slot);
3644 cmd.data0 = mgp->max_intr_slots * sizeof(struct mcp_slot);
3645 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
3647 dev_err(&mgp->pdev->dev, "failed MXGEFW_CMD_SET_INTRQ_SIZE\n");
3652 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_RSS_QUEUES, &cmd, 0);
3656 mgp->num_slices = cmd.data0;
3669 if (mgp->num_slices > myri10ge_max_slices)
3670 mgp->num_slices = myri10ge_max_slices;
3676 mgp->msix_vectors = kcalloc(mgp->num_slices, sizeof(*mgp->msix_vectors),
3678 if (mgp->msix_vectors == NULL)
3680 for (i = 0; i < mgp->num_slices; i++) {
3681 mgp->msix_vectors[i].entry = i;
3684 while (mgp->num_slices > 1) {
3685 mgp->num_slices = rounddown_pow_of_two(mgp->num_slices);
3686 if (mgp->num_slices == 1)
3689 mgp->msix_vectors,
3690 mgp->num_slices,
3691 mgp->num_slices);
3697 if (status == mgp->num_slices) {
3702 mgp->num_slices = status;
3707 if (mgp->msix_vectors != NULL) {
3708 kfree(mgp->msix_vectors);
3709 mgp->msix_vectors = NULL;
3713 mgp->num_slices = 1;
3714 set_fw_name(mgp, old_fw, old_allocated);
3715 myri10ge_load_firmware(mgp, 0);
3732 struct myri10ge_priv *mgp;
3740 netdev = alloc_etherdev_mq(sizeof(*mgp), MYRI10GE_MAX_SLICES);
3746 mgp = netdev_priv(netdev);
3747 mgp->dev = netdev;
3748 mgp->pdev = pdev;
3749 mgp->pause = myri10ge_flow_control;
3750 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
3751 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
3752 mgp->board_number = board_number;
3753 init_waitqueue_head(&mgp->down_wq);
3763 mgp->vendor_specific_offset
3790 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3791 &mgp->cmd_bus, GFP_KERNEL);
3792 if (!mgp->cmd) {
3797 mgp->board_span = pci_resource_len(pdev, 0);
3798 mgp->iomem_base = pci_resource_start(pdev, 0);
3799 mgp->wc_cookie = arch_phys_wc_add(mgp->iomem_base, mgp->board_span);
3800 mgp->sram = ioremap_wc(mgp->iomem_base, mgp->board_span);
3801 if (mgp->sram == NULL) {
3803 mgp->board_span, mgp->iomem_base);
3808 swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET)) & 0xffffc;
3810 mgp->sram_size = swab32(readl(mgp->sram + ss_offset));
3811 if (mgp->sram_size > mgp->board_span ||
3812 mgp->sram_size <= MYRI10GE_FW_OFFSET) {
3815 mgp->sram_size, mgp->board_span);
3819 memcpy_fromio(mgp->eeprom_strings,
3820 mgp->sram + mgp->sram_size, MYRI10GE_EEPROM_STRINGS_SIZE);
3821 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3822 status = myri10ge_read_mac_addr(mgp);
3827 netdev->dev_addr[i] = mgp->mac_addr[i];
3829 myri10ge_select_firmware(mgp);
3831 status = myri10ge_load_firmware(mgp, 1);
3836 myri10ge_probe_slices(mgp);
3837 status = myri10ge_alloc_slices(mgp);
3842 netif_set_real_num_tx_queues(netdev, mgp->num_slices);
3843 netif_set_real_num_rx_queues(netdev, mgp->num_slices);
3844 status = myri10ge_reset(mgp);
3850 myri10ge_setup_dca(mgp);
3852 pci_set_drvdata(pdev, mgp);
3866 netdev->hw_features = mgp->features | NETIF_F_RXCSUM;
3876 netdev->vlan_features |= mgp->features;
3877 if (mgp->fw_ver_tiny < 37)
3879 if (mgp->fw_ver_tiny < 32)
3884 status = myri10ge_request_irq(mgp);
3887 myri10ge_free_irq(mgp);
3894 timer_setup(&mgp->watchdog_timer, myri10ge_watchdog_timer, 0);
3897 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
3903 if (mgp->msix_enabled)
3905 mgp->num_slices, mgp->tx_boundary, mgp->fw_name,
3906 (mgp->wc_cookie > 0 ? "Enabled" : "Disabled"));
3909 mgp->msi_enabled ? "MSI" : "xPIC",
3910 pdev->irq, mgp->tx_boundary, mgp->fw_name,
3911 (mgp->wc_cookie > 0 ? "Enabled" : "Disabled"));
3920 myri10ge_free_slices(mgp);
3923 kfree(mgp->msix_vectors);
3924 myri10ge_dummy_rdma(mgp, 0);
3927 if (mgp->mac_addr_string != NULL)
3930 mgp->mac_addr_string, mgp->serial_number);
3931 iounmap(mgp->sram);
3934 arch_phys_wc_del(mgp->wc_cookie);
3935 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3936 mgp->cmd, mgp->cmd_bus);
3942 set_fw_name(mgp, NULL, false);
3956 struct myri10ge_priv *mgp;
3959 mgp = pci_get_drvdata(pdev);
3960 if (mgp == NULL)
3963 cancel_work_sync(&mgp->watchdog_work);
3964 netdev = mgp->dev;
3968 myri10ge_teardown_dca(mgp);
3970 myri10ge_dummy_rdma(mgp, 0);
3975 iounmap(mgp->sram);
3976 arch_phys_wc_del(mgp->wc_cookie);
3977 myri10ge_free_slices(mgp);
3978 kfree(mgp->msix_vectors);
3979 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3980 mgp->cmd, mgp->cmd_bus);
3982 set_fw_name(mgp, NULL, false);