Lines Matching refs:ctx

20 static int encx24j600_switch_bank(struct encx24j600_context *ctx,
26 	ret = spi_write(ctx->spi, &bank_opcode, 1);
28 		ctx->bank = bank;
33 static int encx24j600_cmdn(struct encx24j600_context *ctx, u8 opcode,
43 	return spi_sync(ctx->spi, &m);
48 	struct encx24j600_context *ctx = context;
50 	mutex_lock(&ctx->mutex);
55 	struct encx24j600_context *ctx = context;
57 	mutex_unlock(&ctx->mutex);
63 	struct encx24j600_context *ctx = context;
73 		if ((banked_reg < 0x16) && (ctx->bank != bank))
74 			ret = encx24j600_switch_bank(ctx, bank);
106 	ret = spi_write_then_read(ctx->spi, tx_buf, i, val, len);
111 static int regmap_encx24j600_sfr_update(struct encx24j600_context *ctx,
127 		if ((banked_reg < 0x16) && (ctx->bank != bank))
128 			ret = encx24j600_switch_bank(ctx, bank);
165 	return spi_sync(ctx->spi, &m);
171 	struct encx24j600_context *ctx = context;
173 	return regmap_encx24j600_sfr_update(ctx, reg, val, len, WCRU, WCRCODE);
176 static int regmap_encx24j600_sfr_set_bits(struct encx24j600_context *ctx,
179 	return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFSU, BFSCODE);
182 static int regmap_encx24j600_sfr_clr_bits(struct encx24j600_context *ctx,
185 	return regmap_encx24j600_sfr_update(ctx, reg, &val, 1, BFCU, BFCCODE);
192 	struct encx24j600_context *ctx = context;
202 		ret = regmap_encx24j600_sfr_set_bits(ctx, reg, set_mask);
207 		ret = regmap_encx24j600_sfr_set_bits(ctx, reg + 1, set_mask);
210 		ret = regmap_encx24j600_sfr_clr_bits(ctx, reg, clr_mask);
215 		ret = regmap_encx24j600_sfr_clr_bits(ctx, reg + 1, clr_mask);
223 	struct encx24j600_context *ctx = context;
226 		return encx24j600_cmdn(ctx, reg, data, count);
229 	return spi_write(ctx->spi, &reg, 1);
235 	struct encx24j600_context *ctx = context;
240 	return spi_write_then_read(ctx->spi, &reg, sizeof(reg), data, count);
348 	struct encx24j600_context *ctx = context;
353 	ret = regmap_write(ctx->regmap, MIREGADR, reg);
357 	ret = regmap_write(ctx->regmap, MICMD, MIIRD);
362 	while (((ret = regmap_read(ctx->regmap, MISTAT, &mistat)) == 0) &&
369 	ret = regmap_write(ctx->regmap, MICMD, 0);
373 	ret = regmap_read(ctx->regmap, MIRD, val);
386 	struct encx24j600_context *ctx = context;
391 	ret = regmap_write(ctx->regmap, MIREGADR, reg);
395 	ret = regmap_write(ctx->regmap, MIWR, val);
400 	while (((ret = regmap_read(ctx->regmap, MISTAT, &mistat)) == 0) &&
501 				struct encx24j600_context *ctx)
503 	mutex_init(&ctx->mutex);
504 	regcfg.lock_arg = ctx;
505 	ctx->regmap = devm_regmap_init(dev, &regmap_encx24j600, ctx, &regcfg);
506 	if (IS_ERR(ctx->regmap))
507 		return PTR_ERR(ctx->regmap);
508 	ctx->phymap = devm_regmap_init(dev, &phymap_encx24j600, ctx, &phycfg);
509 	if (IS_ERR(ctx->phymap))
510 		return PTR_ERR(ctx->phymap);