Lines Matching refs:rx_cfg
1235 * @rx_cfg: Cached receive control settings.
1275 u32 rx_cfg;
3208 u32 rx_cfg;
3211 rx_cfg = hw->rx_cfg;
3214 hw->rx_cfg |= DMA_RX_FLOW_ENABLE;
3216 hw->rx_cfg &= ~DMA_RX_FLOW_ENABLE;
3222 if (rx_cfg != hw->rx_cfg)
3223 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3778 hw->rx_cfg = (DMA_RX_BROADCAST | DMA_RX_UNICAST |
3780 hw->rx_cfg |= KS884X_DMA_RX_MULTICAST;
3783 hw->rx_cfg |= (DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
3786 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
3788 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
3887 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);
3911 writel((hw->rx_cfg & ~DMA_RX_ENABLE), hw->io + KS_DMA_RX_CTRL);
4205 hw->rx_cfg |= DMA_RX_ALL_MULTICAST;
4207 hw->rx_cfg &= ~DMA_RX_ALL_MULTICAST;
4226 hw->rx_cfg |= DMA_RX_PROMISCUOUS;
4228 hw->rx_cfg &= ~DMA_RX_PROMISCUOUS;
5015 if (hw->rx_cfg & (DMA_RX_CSUM_UDP | DMA_RX_CSUM_TCP))
5211 if (hw->enabled && (hw->rx_cfg & DMA_RX_ENABLE)) {
5422 hw->rx_cfg |= DMA_RX_ERROR;
5425 hw->rx_cfg &= ~DMA_RX_ERROR;
6330 (hw->rx_cfg & DMA_RX_FLOW_ENABLE) ? 1 : 0;
6583 hw->rx_cfg |= DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP;
6585 hw->rx_cfg &= ~(DMA_RX_CSUM_TCP | DMA_RX_CSUM_IP);
6588 writel(hw->rx_cfg, hw->io + KS_DMA_RX_CTRL);