Lines Matching refs:data
923 u32 data;
929 u32 data;
933 * struct ksz_hw_desc - Hardware descriptor data structure
947 * struct ksz_sw_desc - Software descriptor data structure
959 * struct ksz_dma_buf - OS dependent DMA buffer data structure
975 * @dma_buf: Operating system dependent data structure to hold physical
987 * struct ksz_desc_info - Descriptor information data structure
1027 * struct ksz_mac_table - Static MAC table data structure
1049 * struct ksz_vlan_table - VLAN table data structure
1113 * struct ksz_port_mib - Port MIB data structure
1142 * struct ksz_port_cfg - Port configuration data structure
1160 * struct ksz_switch - KSZ8842 switch data structure
1191 * struct ksz_port_info - Port information data structure
1224 * struct ksz_hw - KSZ884X hardware data structure
1243 * @tx_size: Transmit data size. Used for TX optimization.
1316 * struct ksz_port - Virtual port data structure
1351 * struct ksz_timer_info - Timer information data structure
1365 * struct ksz_shared_mem - OS dependent shared memory data structure
1381 * struct ksz_counter_info - OS dependent counter information data structure
1393 * struct dev_info - Network device information data structure
1448 * struct dev_priv - Network device private data structure
1595 desc->phw->ctrl.data = cpu_to_le32(status.data);
1601 if (desc->sw.buf_size != desc->sw.buf.data) {
1602 desc->sw.buf_size = desc->sw.buf.data;
1603 desc->phw->buf.data = cpu_to_le32(desc->sw.buf.data);
1605 desc->phw->ctrl.data = cpu_to_le32(desc->sw.ctrl.data);
1614 (*desc)->sw.buf.data &= ~KS_DESC_RX_MASK;
1634 (*desc)->sw.buf.data &= ~KS_DESC_TX_MASK;
1658 * sw_r_table - read 4 bytes of data from switch table
1662 * @data: Buffer to store the read data.
1664 * This routine reads 4 bytes of data from the table of the switch.
1665 * Hardware interrupts are disabled to minimize corruption of read data.
1667 static void sw_r_table(struct ksz_hw *hw, int table, u16 addr, u32 *data)
1678 *data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1684 * sw_w_table_64 - write 8 bytes of data to the switch table
1688 * @data_hi: The high part of data to be written (bit63 ~ bit32).
1689 * @data_lo: The low part of data to be written (bit31 ~ bit0).
1691 * This routine writes 8 bytes of data to the table of the switch.
1692 * Hardware interrupts are disabled to minimize corruption of written data.
1725 * calls sw_w_table_64() to write the data.
1760 * sw_r_table() to get the data.
1767 u32 data;
1769 sw_r_table(hw, TABLE_VLAN, addr, &data);
1770 if (data & VLAN_TABLE_VALID) {
1771 *vid = (u16)(data & VLAN_TABLE_VID);
1772 *fid = (u8)((data & VLAN_TABLE_FID) >> VLAN_TABLE_FID_SHIFT);
1773 *member = (u8)((data & VLAN_TABLE_MEMBERSHIP) >>
1788 * Hardware interrupts are disabled to minimize corruption of read data.
1792 u32 data;
1806 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1808 if (data & MIB_COUNTER_VALID) {
1809 if (data & MIB_COUNTER_OVERFLOW)
1811 *cnt += data & MIB_COUNTER_VALUE;
1827 * Hardware interrupts are disabled to minimize corruption of read data.
1832 u32 data;
1846 data = readl(hw->io + KS884X_ACC_DATA_0_OFFSET);
1850 data &= MIB_PACKET_DROPPED;
1852 if (data != cur) {
1853 *last = data;
1854 if (data < cur)
1855 data += MIB_PACKET_DROPPED + 1;
1856 data -= cur;
1857 *cnt += data;
1929 * @bits: The data bits to check.
1939 u16 data;
1943 data = readw(hw->io + addr);
1944 return (data & bits) == bits;
1952 * @bits: The data bits to set.
1961 u16 data;
1965 data = readw(hw->io + addr);
1967 data |= bits;
1969 data &= ~bits;
1970 writew(data, hw->io + addr);
1987 u16 data;
1990 data = readw(hw->io + addr);
1991 data >>= shift;
1992 return (data & bit) == bit;
2008 u16 data;
2011 data = readw(hw->io + addr);
2014 data |= bits;
2016 data &= ~bits;
2017 writew(data, hw->io + addr);
2025 * @data: Buffer to store the data.
2029 static void port_r8(struct ksz_hw *hw, int port, int offset, u8 *data)
2035 *data = readb(hw->io + addr);
2043 * @data: Buffer to store the data.
2047 static void port_r16(struct ksz_hw *hw, int port, int offset, u16 *data)
2053 *data = readw(hw->io + addr);
2061 * @data: Data to write.
2065 static void port_w16(struct ksz_hw *hw, int port, int offset, u16 data)
2071 writew(data, hw->io + addr);
2078 * @bits: The data bits to check.
2087 u16 data;
2089 data = readw(hw->io + addr);
2090 return (data & bits) == bits;
2097 * @bits: The data bits to set.
2104 u16 data;
2106 data = readw(hw->io + addr);
2108 data |= bits;
2110 data &= ~bits;
2111 writew(data, hw->io + addr);
2143 u16 data;
2149 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2150 data &= ~(BROADCAST_STORM_RATE_LO | BROADCAST_STORM_RATE_HI);
2151 data |= ((value & 0x00FF) << 8) | ((value & 0xFF00) >> 8);
2152 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2165 u16 data;
2167 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2168 num = (data & BROADCAST_STORM_RATE_HI);
2170 num |= (data & BROADCAST_STORM_RATE_LO) >> 8;
2546 u16 data;
2553 port_r16(hw, port, KS8842_PORT_CTRL_1_OFFSET, &data);
2554 data &= ~PORT_BASED_PRIORITY_MASK;
2555 data |= prio << PORT_BASED_PRIORITY_SHIFT;
2556 port_w16(hw, port, KS8842_PORT_CTRL_1_OFFSET, data);
2671 u8 data;
2676 data = readb(hw->io + addr);
2677 data &= ~PORT_VLAN_MEMBERSHIP;
2678 data |= (member & PORT_MASK);
2679 writeb(data, hw->io + addr);
2726 u16 data;
2729 data = readw(hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2730 data |= SWITCH_FLOW_CTRL;
2731 writew(data, hw->io + KS8842_SWITCH_CTRL_3_OFFSET);
2733 data = readw(hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2736 data |= SWITCH_AGGR_BACKOFF;
2739 data |= SWITCH_AGING_ENABLE;
2740 data |= SWITCH_LINK_AUTO_AGING;
2743 data |= SWITCH_FAST_AGING;
2745 data &= ~SWITCH_FAST_AGING;
2746 writew(data, hw->io + KS8842_SWITCH_CTRL_1_OFFSET);
2748 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2751 data |= NO_EXC_COLLISION_DROP;
2752 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
2774 u16 data;
2776 port_r16(hw, port, KS8842_PORT_CTRL_2_OFFSET, &data);
2779 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2780 data |= PORT_LEARN_DISABLE;
2787 data &= ~PORT_TX_ENABLE;
2788 data |= PORT_RX_ENABLE;
2789 data |= PORT_LEARN_DISABLE;
2792 data &= ~PORT_TX_ENABLE;
2793 data |= PORT_RX_ENABLE;
2794 data &= ~PORT_LEARN_DISABLE;
2797 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2798 data &= ~PORT_LEARN_DISABLE;
2805 data &= ~(PORT_TX_ENABLE | PORT_RX_ENABLE);
2806 data |= PORT_LEARN_DISABLE;
2809 data |= (PORT_TX_ENABLE | PORT_RX_ENABLE);
2810 data |= PORT_LEARN_DISABLE;
2813 port_w16(hw, port, KS8842_PORT_CTRL_2_OFFSET, data);
2898 static inline void hw_r_phy_ctrl(struct ksz_hw *hw, int phy, u16 *data)
2900 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2903 static inline void hw_w_phy_ctrl(struct ksz_hw *hw, int phy, u16 data)
2905 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2908 static inline void hw_r_phy_link_stat(struct ksz_hw *hw, int phy, u16 *data)
2910 *data = readw(hw->io + phy + KS884X_PHY_STATUS_OFFSET);
2913 static inline void hw_r_phy_auto_neg(struct ksz_hw *hw, int phy, u16 *data)
2915 *data = readw(hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2918 static inline void hw_w_phy_auto_neg(struct ksz_hw *hw, int phy, u16 data)
2920 writew(data, hw->io + phy + KS884X_PHY_AUTO_NEG_OFFSET);
2923 static inline void hw_r_phy_rem_cap(struct ksz_hw *hw, int phy, u16 *data)
2925 *data = readw(hw->io + phy + KS884X_PHY_REMOTE_CAP_OFFSET);
2928 static inline void hw_r_phy_crossover(struct ksz_hw *hw, int phy, u16 *data)
2930 *data = readw(hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2933 static inline void hw_w_phy_crossover(struct ksz_hw *hw, int phy, u16 data)
2935 writew(data, hw->io + phy + KS884X_PHY_CTRL_OFFSET);
2938 static inline void hw_r_phy_polarity(struct ksz_hw *hw, int phy, u16 *data)
2940 *data = readw(hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2943 static inline void hw_w_phy_polarity(struct ksz_hw *hw, int phy, u16 data)
2945 writew(data, hw->io + phy + KS884X_PHY_PHY_CTRL_OFFSET);
2948 static inline void hw_r_phy_link_md(struct ksz_hw *hw, int phy, u16 *data)
2950 *data = readw(hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2953 static inline void hw_w_phy_link_md(struct ksz_hw *hw, int phy, u16 data)
2955 writew(data, hw->io + phy + KS884X_PHY_LINK_MD_OFFSET);
2959 * hw_r_phy - read data from PHY register
2963 * @val: Buffer to store the read data.
2965 * This routine reads data from the PHY register.
2976 * port_w_phy - write data to PHY register
2980 * @val: Word data to write.
2982 * This routine writes data to the PHY register.
3010 u16 data;
3012 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3013 data &= ~gpio;
3014 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
3019 u16 data;
3021 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3022 data |= gpio;
3023 writew(data, hw->io + KS884X_EEPROM_CTRL_OFFSET);
3028 u16 data;
3030 data = readw(hw->io + KS884X_EEPROM_CTRL_OFFSET);
3031 return (u8)(data & gpio);
3059 static void spi_w(struct ksz_hw *hw, u16 data)
3064 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3070 static void spi_reg(struct ksz_hw *hw, u8 data, u8 reg)
3080 (data & (0x01 << i)) ? raise_gpio(hw, EEPROM_DATA_OUT) :
3101 /* User defined EEPROM data */
3111 * Return the data value.
3115 u16 data;
3120 data = spi_r(hw);
3124 return data;
3131 * @data: The data value.
3135 static void eeprom_write(struct ksz_hw *hw, u8 reg, u16 data)
3165 spi_w(hw, data);
3285 u16 data;
3297 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3306 local = (u8) data;
3330 &data);
3333 determine_flow_ctrl(hw, port, data, status);
3371 u16 data;
3378 port_r16(hw, p, KS884X_PORT_CTRL_4_OFFSET, &data);
3383 cfg = data;
3385 data |= PORT_AUTO_NEG_ENABLE;
3386 data = advertised_flow_ctrl(port, data);
3388 data |= PORT_AUTO_NEG_100BTX_FD | PORT_AUTO_NEG_100BTX |
3394 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3397 data &= ~(PORT_AUTO_NEG_10BT_FD |
3400 data &= ~(PORT_AUTO_NEG_100BTX_FD |
3403 data &= ~(PORT_AUTO_NEG_100BTX |
3406 if (data != cfg) {
3407 data |= PORT_AUTO_NEG_RESTART;
3408 port_w16(hw, p, KS884X_PORT_CTRL_4_OFFSET, data);
3422 u16 data;
3429 hw_r_phy_ctrl(hw, phy, &data);
3431 data &= ~PHY_AUTO_NEG_ENABLE;
3434 data &= ~PHY_SPEED_100MBIT;
3436 data |= PHY_SPEED_100MBIT;
3438 data &= ~PHY_FULL_DUPLEX;
3440 data |= PHY_FULL_DUPLEX;
3441 hw_w_phy_ctrl(hw, phy, data);
3472 u16 data;
3476 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3477 return (data & PCI_PM_CTRL_PME_STATUS) == PCI_PM_CTRL_PME_STATUS;
3490 u16 data;
3496 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3497 data |= PCI_PM_CTRL_PME_STATUS;
3498 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3512 u16 data;
3516 pci_read_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, &data);
3517 data &= ~PCI_PM_CTRL_STATE_MASK;
3519 data |= PCI_PM_CTRL_PME_ENABLE | PCI_D3hot;
3521 data &= ~PCI_PM_CTRL_PME_ENABLE;
3522 pci_write_config_word(pdev, pdev->pm_cap + PCI_PM_CTRL, data);
3535 u16 data;
3537 data = readw(hw->io + KS8841_WOL_CTRL_OFFSET);
3539 data |= frame;
3541 data &= ~frame;
3542 writew(data, hw->io + KS8841_WOL_CTRL_OFFSET);
3552 * @pattern: The frame data.
3564 u8 data[64];
3580 data[to++] = pattern[from];
3602 crc = ether_crc(to, data);
3711 u16 data;
3718 data = readw(hw->io + KS884X_CHIP_ID_OFFSET);
3720 revision = (data & KS884X_REVISION_MASK) >> KS884X_REVISION_SHIFT;
3721 data &= KS884X_CHIP_ID_MASK_41;
3722 if (REG_CHIP_ID_41 == data)
3724 else if (REG_CHIP_ID_42 == data)
3764 u16 data;
3767 data = readw(hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3768 data &= ~LED_MODE;
3769 data |= SET_DEFAULT_LED;
3770 writew(data, hw->io + KS8842_SWITCH_CTRL_5_OFFSET);
3844 previous->phw->buf.data = cpu_to_le32(previous->sw.buf.data);
3986 /* Cannot hold on too much data. */
4662 dma_buf->dma = dma_map_single(&hw_priv->pdev->dev, skb->data,
4703 dma_buf->dma = dma_map_single(&hw_priv->pdev->dev, skb->data,
4750 status.data = le32_to_cpu(desc->phw->ctrl.data);
4839 if (skb_end_pointer(skb) - skb->data >= 50) {
4840 memset(&skb->data[skb->len], 0, 50 - skb->len);
4846 memcpy(skb->data, org_skb->data, org_skb->len);
4847 memset(&skb->data[org_skb->len], 0,
4870 skb_copy_and_csum_dev(org_skb, skb->data);
4997 /* skb->data != skb->head */
5010 skb_put_data(skb, dma_buf->skb->data, packet_len);
5043 status.data = le32_to_cpu(desc->phw->ctrl.data);
5079 status.data = le32_to_cpu(desc->phw->ctrl.data);
5124 status.data = le32_to_cpu(desc->phw->ctrl.data);
5144 if (!status.rx.error || (status.data &
5281 u32 data;
5285 data = readl(hw->io + KS_DMA_TX_CTRL);
5286 if (!(data & DMA_TX_ENABLE))
5412 u32 data;
5414 data = readw(hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5416 data |= SWITCH_HUGE_PACKET;
5418 data &= ~SWITCH_HUGE_PACKET;
5419 writew(data, hw->io + KS8842_SWITCH_CTRL_2_OFFSET);
5827 struct mii_ioctl_data *data = if_mii(ifr);
5835 data->phy_id = priv->id;
5840 if (data->phy_id != priv->id || data->reg_num >= 6)
5843 hw_r_phy(hw, port->linked->port_id, data->reg_num,
5844 &data->val_out);
5851 else if (data->phy_id != priv->id || data->reg_num >= 6)
5854 hw_w_phy(hw, port->linked->port_id, data->reg_num,
5855 data->val_in);
6068 * @info: Ethtool driver info data structure.
6120 * @regs: Ethtool registers data structure.
6159 * @wol: Ethtool Wake-on-LAN data structure.
6177 * @wol: Ethtool Wake-on-LAN data structure.
6249 * netdev_get_eeprom - get EEPROM data
6251 * @eeprom: Ethtool EEPROM data structure.
6252 * @data: Buffer to store the EEPROM data.
6254 * This function dumps the EEPROM data in the provided buffer.
6259 struct ethtool_eeprom *eeprom, u8 *data)
6271 memcpy(data, &eeprom_byte[eeprom->offset], eeprom->len);
6277 * netdev_set_eeprom - write EEPROM data
6279 * @eeprom: Ethtool EEPROM data structure.
6280 * @data: Data buffer.
6282 * This function modifies the EEPROM data one byte at a time.
6287 struct ethtool_eeprom *eeprom, u8 *data)
6303 memcpy(&eeprom_byte[eeprom->offset], data, eeprom->len);
6316 * @pause: Ethtool PAUSE settings data structure.
6346 * @pause: Ethtool PAUSE settings data structure.
6394 * @ring: Ethtool RING settings data structure.
6499 * @stats: Ethtool statistics data structure.
6500 * @data: Buffer to store the statistics.
6505 struct ethtool_stats *stats, u64 *data)
6560 *data++ = counter[i];
6888 u16 data[3];
6892 data[i] = eeprom_read(hw, i + EEPROM_DATA_OTHER_MAC_ADDR);
6893 if ((data[0] || data[1] || data[2]) && data[0] != 0xffff) {
6894 sw->other_addr[5] = (u8) data[0];
6895 sw->other_addr[4] = (u8)(data[0] >> 8);
6896 sw->other_addr[3] = (u8) data[1];
6897 sw->other_addr[2] = (u8)(data[1] >> 8);
6898 sw->other_addr[1] = (u8) data[2];
6899 sw->other_addr[0] = (u8)(data[2] >> 8);