Lines Matching refs:caps
300 dev->caps.reserved_uars =
312 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
313 for (i = 0; i < dev->caps.num_ports - 1; i++) {
321 for (i = 0; i < dev->caps.num_ports; i++) {
322 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
335 for (i = 1; i <= dev->caps.num_ports; ++i)
336 dev->caps.port_mask[i] = dev->caps.port_type[i];
348 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
364 struct mlx4_caps *dev_cap = &dev->caps;
400 dev->caps.vl_cap[port] = port_cap->max_vl;
401 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu;
407 dev->caps.gid_table_len[port] = port_cap->max_gids;
408 dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
409 dev->caps.port_width_cap[port] = port_cap->max_port_width;
410 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu;
411 dev->caps.max_tc_eth = port_cap->max_tc_eth;
412 dev->caps.def_mac[port] = port_cap->def_mac;
413 dev->caps.supported_type[port] = port_cap->supported_port_types;
414 dev->caps.suggested_type[port] = port_cap->suggested_type;
415 dev->caps.default_sense[port] = port_cap->default_sense;
416 dev->caps.trans_type[port] = port_cap->trans_type;
417 dev->caps.vendor_oui[port] = port_cap->vendor_oui;
418 dev->caps.wavelength[port] = port_cap->wavelength;
419 dev->caps.trans_code[port] = port_cap->trans_code;
439 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS))
444 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
448 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
451 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
488 dev->caps.num_ports = dev_cap->num_ports;
489 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
491 dev->caps.num_sys_eqs :
493 for (i = 1; i <= dev->caps.num_ports; ++i) {
501 dev->caps.map_clock_to_user = dev_cap->map_clock_to_user;
502 dev->caps.uar_page_size = PAGE_SIZE;
503 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
504 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
505 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
506 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
507 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
508 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
509 dev->caps.max_wqes = dev_cap->max_qp_sz;
510 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
511 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
512 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
513 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
514 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
515 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
520 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
521 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
522 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
523 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
524 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
526 dev->caps.reserved_pds = dev_cap->reserved_pds;
527 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
529 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
531 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
533 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
534 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
535 dev->caps.flags = dev_cap->flags;
536 dev->caps.flags2 = dev_cap->flags2;
537 dev->caps.bmme_flags = dev_cap->bmme_flags;
538 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
539 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
540 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
541 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
542 dev->caps.wol_port[1] = dev_cap->wol_port[1];
543 dev->caps.wol_port[2] = dev_cap->wol_port[2];
544 dev->caps.health_buffer_addrs = dev_cap->health_buffer_addrs;
559 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) {
571 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN;
576 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
579 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
582 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC;
583 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
585 dev->caps.log_num_macs = log_num_mac;
586 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
589 for (i = 1; i <= dev->caps.num_ports; ++i) {
590 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
591 if (dev->caps.supported_type[i]) {
593 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
594 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
596 else if (dev->caps.supported_type[i] ==
598 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
604 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
607 dev->caps.port_type[i] = port_type_array[i - 1];
617 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
618 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
619 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
626 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
628 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
631 dev->caps.port_type[i] = sensed_port;
633 dev->caps.possible_type[i] = dev->caps.port_type[i];
636 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
637 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
639 i, 1 << dev->caps.log_num_macs);
641 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
642 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
644 i, 1 << dev->caps.log_num_vlans);
648 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) &&
653 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP;
656 dev->caps.max_counters = dev_cap->max_counters;
658 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
659 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
660 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
661 (1 << dev->caps.log_num_macs) *
662 (1 << dev->caps.log_num_vlans) *
663 dev->caps.num_ports;
664 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
667 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
668 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
670 dev->caps.dmfs_high_rate_qpn_base =
671 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
674 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
675 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
676 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
677 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
679 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
680 dev->caps.dmfs_high_rate_qpn_base =
681 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
682 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
685 dev->caps.rl_caps = dev_cap->rl_caps;
687 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
688 dev->caps.dmfs_high_rate_qpn_range;
690 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
691 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
692 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
693 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
695 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
701 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
702 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
714 if ((dev->caps.flags &
717 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
721 dev->caps.alloc_res_qp_mask =
722 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
725 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) &&
726 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
729 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
733 dev->caps.alloc_res_qp_mask = 0;
846 dev->caps.steering_mode = hca_param->steering_mode;
847 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
848 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
849 dev->caps.fs_log_max_ucast_qp_range_size =
852 dev->caps.num_qp_per_mgm =
856 mlx4_steering_mode_str(dev->caps.steering_mode));
861 kfree(dev->caps.spec_qps);
862 dev->caps.spec_qps = NULL;
868 struct mlx4_caps *caps = &dev->caps;
872 caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL);
874 if (!func_cap || !caps->spec_qps) {
880 for (i = 1; i <= caps->num_ports; ++i) {
887 caps->spec_qps[i - 1] = func_cap->spec_qps;
888 caps->port_mask[i] = caps->port_type[i];
889 caps->phys_port_id[i] = func_cap->phys_port_id;
891 &caps->gid_table_len[i],
892 &caps->pkey_table_len[i]);
939 dev->caps.hca_core_clock = hca_param->hca_core_clock;
941 dev->caps.max_qp_dest_rdma = 1 << hca_param->log_rd_per_qp;
952 page_size = ~dev->caps.page_size_cap + 1;
979 dev->caps.uar_page_size = PAGE_SIZE;
997 dev->caps.num_ports = func_cap->num_ports;
1003 dev->caps.num_qps = 1 << hca_param->log_num_qps;
1004 dev->caps.num_srqs = 1 << hca_param->log_num_srqs;
1005 dev->caps.num_cqs = 1 << hca_param->log_num_cqs;
1006 dev->caps.num_mpts = 1 << hca_param->log_mpt_sz;
1007 dev->caps.num_eqs = func_cap->max_eq;
1008 dev->caps.reserved_eqs = func_cap->reserved_eq;
1009 dev->caps.reserved_lkey = func_cap->reserved_lkey;
1010 dev->caps.num_pds = MLX4_NUM_PDS;
1011 dev->caps.num_mgms = 0;
1012 dev->caps.num_amgms = 0;
1014 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
1016 dev->caps.num_ports, MLX4_MAX_PORTS);
1025 mlx4_err(dev, "Set special QP caps failed. aborting\n");
1029 if (dev->caps.uar_page_size * (dev->caps.num_uars -
1030 dev->caps.reserved_uars) >
1034 dev->caps.uar_page_size * dev->caps.num_uars,
1042 dev->caps.eqe_size = 64;
1043 dev->caps.eqe_factor = 1;
1045 dev->caps.eqe_size = 32;
1046 dev->caps.eqe_factor = 0;
1050 dev->caps.cqe_size = 64;
1051 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1053 dev->caps.cqe_size = 32;
1057 dev->caps.eqe_size = hca_param->eqe_size;
1058 dev->caps.eqe_factor = 0;
1062 dev->caps.cqe_size = hca_param->cqe_size;
1064 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
1067 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
1070 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_USER_MAC_EN;
1078 dev->caps.bf_reg_size)
1079 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
1082 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
1102 for (port = 1; port <= dev->caps.num_ports; port++) {
1103 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
1105 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
1111 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
1126 for (port = 0; port < dev->caps.num_ports; port++) {
1129 if (port_types[port] != dev->caps.port_type[port + 1])
1134 for (port = 1; port <= dev->caps.num_ports; port++) {
1136 dev->caps.port_type[port] = port_types[port - 1];
1167 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1169 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1187 if ((port_type & mdev->caps.supported_type[info->port]) != port_type) {
1199 mdev->caps.possible_type[info->port] = info->tmp_type;
1201 for (i = 0; i < mdev->caps.num_ports; i++) {
1203 mdev->caps.possible_type[i+1];
1205 types[i] = mdev->caps.port_type[i+1];
1208 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1209 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
1210 for (i = 1; i <= mdev->caps.num_ports; i++) {
1211 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1212 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1231 for (i = 0; i < mdev->caps.num_ports; i++)
1316 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1320 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1334 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1348 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1353 for (port = 1; port <= mdev->caps.num_ports; port++) {
1404 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1512 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
1594 cmpt_entry_sz, dev->caps.num_qps,
1595 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1604 cmpt_entry_sz, dev->caps.num_srqs,
1605 dev->caps.reserved_srqs, 0, 0);
1613 cmpt_entry_sz, dev->caps.num_cqs,
1614 dev->caps.reserved_cqs, 0, 0);
1693 * dev->caps.mtt_entry_sz below is really the MTT segment
1696 dev->caps.reserved_mtts =
1697 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1698 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1702 dev->caps.mtt_entry_sz,
1703 dev->caps.num_mtts,
1704 dev->caps.reserved_mtts, 1, 0);
1713 dev->caps.num_mpts,
1714 dev->caps.reserved_mrws, 1, 1);
1723 dev->caps.num_qps,
1724 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1734 dev->caps.num_qps,
1735 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1745 dev->caps.num_qps,
1746 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1756 dev->caps.num_qps,
1757 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1767 dev->caps.num_cqs,
1768 dev->caps.reserved_cqs, 0, 0);
1777 dev->caps.num_srqs,
1778 dev->caps.reserved_srqs, 0, 0);
1794 dev->caps.num_mgms + dev->caps.num_amgms,
1795 dev->caps.num_mgms + dev->caps.num_amgms,
1887 if (!dev->caps.bf_reg_size)
1891 (dev->caps.num_uars << PAGE_SHIFT);
1893 (dev->caps.num_uars << PAGE_SHIFT);
1952 if (!dev->caps.map_clock_to_user) {
2045 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
2122 for (i = 1; i <= dev->caps.num_ports; i++) {
2123 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
2124 dev->caps.gid_table_len[i] =
2127 dev->caps.gid_table_len[i] = 1;
2128 dev->caps.pkey_table_len[i] =
2176 if (dev->caps.dmfs_high_steer_mode ==
2180 dev->caps.dmfs_high_steer_mode =
2194 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
2195 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
2196 dev->caps.fs_log_max_ucast_qp_range_size =
2199 if (dev->caps.dmfs_high_steer_mode !=
2201 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
2202 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
2203 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2204 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
2206 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
2208 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
2209 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2216 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
2219 mlx4_steering_mode_str(dev->caps.steering_mode),
2227 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2229 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
2231 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
2233 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
2242 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2245 for (i = 1; i <= dev->caps.num_ports; i++) {
2249 } else if ((dev->caps.dmfs_high_steer_mode !=
2252 !!(dev->caps.dmfs_high_steer_mode ==
2257 dev->caps.dmfs_high_steer_mode),
2326 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
2328 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
2343 if (dev->caps.steering_mode ==
2355 init_hca->log_uar_sz = ilog2(dev->caps.num_uars) +
2359 init_hca->log_uar_sz = ilog2(dev->caps.num_uars);
2364 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2365 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
2384 dev->caps.num_eqs = dev_cap->max_eqs;
2385 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
2386 dev->caps.reserved_uars = dev_cap->reserved_uars;
2394 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2398 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2400 dev->caps.hca_core_clock =
2407 if (!dev->caps.hca_core_clock) {
2408 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2416 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2421 if (dev->caps.dmfs_high_steer_mode !=
2426 if (dev->caps.dmfs_high_steer_mode ==
2428 dev->caps.dmfs_high_rate_qpn_base =
2429 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2430 dev->caps.dmfs_high_rate_qpn_range =
2436 dev->caps.dmfs_high_steer_mode));
2448 mlx4_err(dev, "Failed to obtain slave caps\n");
2471 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2472 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2509 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2512 if (!dev->caps.max_counters)
2515 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2519 nent_pow2 - dev->caps.max_counters + 1);
2524 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2527 if (!dev->caps.max_counters)
2538 for (port = 0; port < dev->caps.num_ports; port++)
2549 for (port = 0; port < dev->caps.num_ports; port++)
2552 for (port = 0; port < dev->caps.num_ports; port++) {
2584 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2637 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2822 for (port = 1; port <= dev->caps.num_ports; port++) {
2827 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2829 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2843 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2845 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
2848 dev->caps.pkey_table_len[port] : -1);
2913 if (eqn > dev->caps.num_comp_vectors)
2943 int nreq = min3(dev->caps.num_ports *
2945 dev->caps.num_eqs - dev->caps.reserved_eqs,
2966 dev->caps.num_comp_vectors = nreq - 1;
2970 dev->caps.num_ports);
2972 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {
2979 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) {
2981 dev->caps.num_ports);
2993 * (dev->caps.num_comp_vectors / dev->caps.num_ports)
3001 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) &&
3003 (dev->caps.num_comp_vectors / dev->caps.num_ports)) ==
3005 /* If dev->caps.num_comp_vectors < dev->caps.num_ports,
3018 dev->caps.num_comp_vectors = 1;
3025 dev->caps.num_ports);
3045 dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
3048 dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
3123 int num_entries = dev->caps.num_ports;
3144 int num_entries = dev->caps.num_ports;
3553 if (dev->caps.num_ports < 2 &&
3558 dev->caps.num_ports);
3571 dev->caps.num_ports;
3612 dev->caps.num_comp_vectors = 1;
3632 for (port = 1; port <= dev->caps.num_ports; port++) {
4079 for (i = 0; i < dev->caps.num_ports; i++) {
4080 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
4081 dev->persist->curr_port_poss_type[i] = dev->caps.
4090 for (p = 1; p <= dev->caps.num_ports; p++) {
4203 for (i = 0; i < dev->caps.num_ports; i++)
4204 dev->caps.possible_type[i + 1] = poss_types[i];