Lines Matching defs:outbox
207 u32 *outbox;
224 outbox = mailbox->buf;
235 MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET);
237 MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET);
239 MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET);
241 MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET);
243 MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET);
245 MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET);
247 MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET);
328 struct mlx4_cmd_mailbox *outbox,
408 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
419 MLX4_PUT(outbox->buf, qkey,
422 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET);
426 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL);
429 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL);
431 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY);
433 MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY);
435 MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier],
448 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS0_OFFSET);
462 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET);
467 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
470 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
473 MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET);
476 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
478 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
481 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
483 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
486 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
488 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
496 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
498 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
504 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
506 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
510 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
512 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
515 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
517 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
520 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
521 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
525 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
528 MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET);
543 u32 *outbox;
565 outbox = mailbox->buf;
568 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET);
577 MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET);
580 MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET);
584 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET);
587 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET);
590 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET);
593 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET);
596 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET);
599 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET);
603 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP);
606 MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP);
609 MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP);
612 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP);
615 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP);
618 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP);
621 MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET);
624 MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET);
628 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET);
640 MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET);
656 MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET);
670 MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
678 MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET);
686 MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET);
692 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL);
695 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY);
698 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL);
701 MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY);
705 MLX4_GET(func_cap->phys_port_id, outbox,
708 MLX4_GET(func_cap->flags0, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET);
728 u32 *outbox;
836 outbox = mailbox->buf;
844 disable_unsupported_roce_caps(outbox);
845 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAP_CLOCK_TO_USER);
847 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET);
849 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET);
851 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET);
853 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET);
855 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET);
857 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET);
859 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET);
861 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET);
863 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET);
865 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET);
867 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET);
869 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET);
871 MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET);
873 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET);
875 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET);
877 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET);
884 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET);
895 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET);
897 MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET);
899 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
901 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET);
903 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET);
906 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET);
912 MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET);
915 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
918 MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET);
920 MLX4_GET(field, outbox, QUERY_DEV_CAP_SL2VL_EVENT_OFFSET);
923 MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
926 MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET);
928 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
931 MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
932 MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET);
934 MLX4_GET(field, outbox, QUERY_DEV_CAP_WOL_OFFSET);
937 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET);
939 MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET);
941 MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET);
944 MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET);
946 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET);
948 MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET);
956 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET);
958 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET);
961 MLX4_GET(field, outbox, QUERY_DEV_CAP_USER_MAC_EN_OFFSET);
964 MLX4_GET(field, outbox, QUERY_DEV_CAP_SVLAN_BY_QP_OFFSET);
967 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET);
969 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET);
971 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET);
973 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET);
975 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET);
977 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET);
979 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET);
982 MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET);
984 MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET);
986 MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET);
988 MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET);
990 MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET);
992 MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET);
994 MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET);
996 MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET);
998 MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET);
1000 MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET);
1003 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET);
1005 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET);
1007 MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET);
1009 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET);
1011 MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET);
1013 MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
1022 MLX4_GET(dev_cap->bmme_flags, outbox,
1028 MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
1033 MLX4_GET(field, outbox, QUERY_DEV_CAP_PHV_EN_OFFSET);
1039 MLX4_GET(dev_cap->reserved_lkey, outbox,
1041 MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET);
1048 MLX4_GET(field32, outbox, QUERY_DEV_CAP_DIAG_RPRT_PER_PORT);
1051 MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC);
1054 MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN);
1059 MLX4_GET(dev_cap->max_icm_sz, outbox,
1062 MLX4_GET(dev_cap->max_counters, outbox,
1065 MLX4_GET(field32, outbox,
1070 MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox,
1073 MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox,
1077 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET);
1081 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET);
1084 MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET);
1089 MLX4_GET(dev_cap->health_buffer_addrs, outbox,
1092 MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1189 u32 *outbox;
1197 outbox = mailbox->buf;
1207 MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET);
1209 MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET);
1212 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET);
1214 MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET);
1234 MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET);
1240 MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET);
1242 MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET);
1244 MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET);
1247 MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET);
1250 MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET);
1253 MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET);
1254 MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET);
1255 MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET);
1258 MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET);
1259 MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET);
1275 struct mlx4_cmd_mailbox *outbox,
1288 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP,
1293 disable_unsupported_roce_caps(outbox->buf);
1297 MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1316 MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET);
1318 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET);
1321 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET);
1324 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1326 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET);
1329 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN);
1331 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN);
1334 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET);
1336 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET);
1339 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET);
1341 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET);
1344 MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1347 MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET);
1351 MLX4_GET(field, outbox->buf,
1354 MLX4_PUT(outbox->buf, field,
1359 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
1361 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET);
1364 MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1367 MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET);
1370 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
1372 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET);
1376 MLX4_PUT(outbox->buf, field16, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET);
1379 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
1381 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE);
1384 MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
1386 MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CONFIG_DEV_OFFSET);
1409 struct mlx4_cmd_mailbox *outbox,
1437 err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0,
1443 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
1446 MLX4_GET(port_type, outbox->buf,
1469 MLX4_PUT(outbox->buf, port_type,
1476 MLX4_PUT(outbox->buf, short_field,
1480 MLX4_PUT(outbox->buf, short_field,
1491 u32 *outbox;
1505 outbox = mailbox->buf;
1507 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET);
1510 MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET);
1623 u32 *outbox;
1651 outbox = mailbox->buf;
1658 MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET);
1667 MLX4_GET(lg, outbox, QUERY_FW_PPF_ID);
1674 MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET);
1692 MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET);
1701 MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET);
1702 MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET);
1703 MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET);
1709 MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET);
1710 MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET);
1711 MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET);
1714 MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET);
1715 MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET);
1721 MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET);
1722 MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR);
1746 struct mlx4_cmd_mailbox *outbox,
1752 outbuf = outbox->buf;
1753 err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW,
1806 u32 *outbox;
1816 outbox = mailbox->buf;
1823 MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET);
1825 get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4,
2072 __be32 *outbox;
2091 outbox = mailbox->buf;
2100 MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET);
2101 MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
2105 MLX4_GET(qword_field, outbox, INIT_HCA_QPC_BASE_OFFSET);
2107 MLX4_GET(byte_field, outbox, INIT_HCA_LOG_QP_OFFSET);
2109 MLX4_GET(qword_field, outbox, INIT_HCA_SRQC_BASE_OFFSET);
2111 MLX4_GET(byte_field, outbox, INIT_HCA_LOG_SRQ_OFFSET);
2113 MLX4_GET(qword_field, outbox, INIT_HCA_CQC_BASE_OFFSET);
2115 MLX4_GET(byte_field, outbox, INIT_HCA_LOG_CQ_OFFSET);
2117 MLX4_GET(qword_field, outbox, INIT_HCA_ALTC_BASE_OFFSET);
2119 MLX4_GET(qword_field, outbox, INIT_HCA_AUXC_BASE_OFFSET);
2121 MLX4_GET(qword_field, outbox, INIT_HCA_EQC_BASE_OFFSET);
2123 MLX4_GET(byte_field, outbox, INIT_HCA_LOG_EQ_OFFSET);
2125 MLX4_GET(word_field, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET);
2127 MLX4_GET(qword_field, outbox, INIT_HCA_RDMARC_BASE_OFFSET);
2129 MLX4_GET(byte_field, outbox, INIT_HCA_LOG_RD_OFFSET);
2132 MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET);
2136 MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET);
2148 MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET);
2149 MLX4_GET(byte_field, outbox, INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET);
2151 MLX4_GET(byte_field, outbox, INIT_HCA_FS_LOG_TABLE_SZ_OFFSET);
2153 MLX4_GET(byte_field, outbox, INIT_HCA_FS_A0_OFFSET);
2157 MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET);
2158 MLX4_GET(byte_field, outbox, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET);
2160 MLX4_GET(byte_field, outbox, INIT_HCA_LOG_MC_HASH_SZ_OFFSET);
2162 MLX4_GET(byte_field, outbox, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET);
2167 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS);
2174 MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET);
2186 MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET);
2187 MLX4_GET(byte_field, outbox, INIT_HCA_TPT_MW_OFFSET);
2189 MLX4_GET(byte_field, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET);
2191 MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET);
2192 MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET);
2196 MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET);
2197 MLX4_GET(byte_field, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET);
2201 MLX4_GET(byte_field, outbox, INIT_HCA_CACHELINE_SZ_OFFSET);
2213 __be32 *outbox;
2221 outbox = mailbox->buf;
2232 MLX4_GET(dev->caps.hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET);
2256 struct mlx4_cmd_mailbox *outbox,
2354 struct mlx4_cmd_mailbox *outbox,
2609 u32 *outbox;
2617 outbox = mailbox->buf;
2631 MLX4_GET(value[i], outbox, offset[i]);
2643 u32 *outbox;
2655 outbox = mailbox->buf;
2667 MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H);
2668 MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L);
2710 u32 *outbox;
2731 outbox = mailbox->buf;
2742 MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET);
2743 MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET);
2744 MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET);
2755 mgm = (struct mlx4_mgm *)((u8 *)(outbox) +
2792 memset(outbox, 0, 0xffc);
2912 * Returns 0 on success and copies outbox mlx4_access_reg data
2919 struct mlx4_cmd_mailbox *inbox, *outbox;
2927 outbox = mlx4_alloc_cmd_mailbox(dev);
2928 if (IS_ERR(outbox)) {
2930 return PTR_ERR(outbox);
2934 outbuf = outbox->buf;
2947 err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0,
2964 mlx4_free_cmd_mailbox(dev, outbox);
2996 struct mlx4_cmd_mailbox *outbox,
3016 return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier,