Lines Matching refs:ss
16 int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
21 ss->ana_rgc3 = ana_rgc3;
28 ss->regmap[i] = syscon_node_to_regmap(np);
30 if (IS_ERR(ss->regmap[i]))
31 return PTR_ERR(ss->regmap[i]);
37 int mtk_sgmii_setup_mode_an(struct mtk_sgmii *ss, int id)
41 if (!ss->regmap[id])
45 regmap_write(ss->regmap[id], SGMSYS_PCS_LINK_TIMER,
48 regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val);
50 regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
52 regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val);
54 regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val);
56 regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val);
58 regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val);
63 int mtk_sgmii_setup_mode_force(struct mtk_sgmii *ss, int id,
68 if (!ss->regmap[id])
71 regmap_read(ss->regmap[id], ss->ana_rgc3, &val);
75 regmap_write(ss->regmap[id], ss->ana_rgc3, val);
78 regmap_read(ss->regmap[id], SGMSYS_PCS_CONTROL_1, &val);
80 regmap_write(ss->regmap[id], SGMSYS_PCS_CONTROL_1, val);
83 regmap_read(ss->regmap[id], SGMSYS_SGMII_MODE, &val);
102 regmap_write(ss->regmap[id], SGMSYS_SGMII_MODE, val);
105 regmap_read(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, &val);
107 regmap_write(ss->regmap[id], SGMSYS_QPHY_PWR_STATE_CTRL, val);
114 struct mtk_sgmii *ss = eth->sgmii;
121 if (!ss->regmap[sid])
124 regmap_read(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, &val);
126 regmap_write(ss->regmap[sid], SGMSYS_PCS_CONTROL_1, val);