Lines Matching defs:reg
314 #define RAM_BUFFER(port, reg) (reg | (port <<6))
389 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
641 /* Y2_PEX_PHY_ADDR/DATA PEX PHY address and data reg (Yukon-2 only) */
665 #define SK_REG(port,reg) (((port)<<7)+(reg))
751 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
782 #define Y2_QADDR(q,reg) (Y2_B8_PREF_REGS + (q) + (reg))
2315 static inline u32 sky2_read32(const struct sky2_hw *hw, unsigned reg)
2317 return readl(hw->regs + reg);
2320 static inline u16 sky2_read16(const struct sky2_hw *hw, unsigned reg)
2322 return readw(hw->regs + reg);
2325 static inline u8 sky2_read8(const struct sky2_hw *hw, unsigned reg)
2327 return readb(hw->regs + reg);
2330 static inline void sky2_write32(const struct sky2_hw *hw, unsigned reg, u32 val)
2332 writel(val, hw->regs + reg);
2335 static inline void sky2_write16(const struct sky2_hw *hw, unsigned reg, u16 val)
2337 writew(val, hw->regs + reg);
2340 static inline void sky2_write8(const struct sky2_hw *hw, unsigned reg, u8 val)
2342 writeb(val, hw->regs + reg);
2346 #define SK_GMAC_REG(port,reg) \
2347 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2350 static inline u16 gma_read16(const struct sky2_hw *hw, unsigned port, unsigned reg)
2352 return sky2_read16(hw, SK_GMAC_REG(port,reg));
2355 static inline u32 gma_read32(struct sky2_hw *hw, unsigned port, unsigned reg)
2357 unsigned base = SK_GMAC_REG(port, reg);
2362 static inline u64 gma_read64(struct sky2_hw *hw, unsigned port, unsigned reg)
2364 unsigned base = SK_GMAC_REG(port, reg);
2373 static inline u32 get_stats32(struct sky2_hw *hw, unsigned port, unsigned reg)
2378 val = gma_read32(hw, port, reg);
2379 } while (gma_read32(hw, port, reg) != val);
2384 static inline u64 get_stats64(struct sky2_hw *hw, unsigned port, unsigned reg)
2389 val = gma_read64(hw, port, reg);
2390 } while (gma_read64(hw, port, reg) != val);
2400 static inline void gma_set_addr(struct sky2_hw *hw, unsigned port, unsigned reg,
2403 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
2404 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
2405 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
2409 static inline u32 sky2_pci_read32(const struct sky2_hw *hw, unsigned reg)
2411 return sky2_read32(hw, Y2_CFG_SPC + reg);
2414 static inline u16 sky2_pci_read16(const struct sky2_hw *hw, unsigned reg)
2416 return sky2_read16(hw, Y2_CFG_SPC + reg);
2419 static inline void sky2_pci_write32(struct sky2_hw *hw, unsigned reg, u32 val)
2421 sky2_write32(hw, Y2_CFG_SPC + reg, val);
2424 static inline void sky2_pci_write16(struct sky2_hw *hw, unsigned reg, u16 val)
2426 sky2_write16(hw, Y2_CFG_SPC + reg, val);