Lines Matching refs:sky2_write32
219 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
252 sky2_write32(hw, B2_GP_IO, reg);
886 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
889 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
892 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
894 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
990 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
1046 sky2_write32(hw, RB_ADDR(q, RB_START), start);
1047 sky2_write32(hw, RB_ADDR(q, RB_END), end);
1048 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
1049 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
1058 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
1059 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
1062 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
1063 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
1078 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1079 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1080 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1081 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1090 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1091 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1092 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1093 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1095 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1274 sky2_write32(sky2->hw,
1290 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1299 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1303 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1306 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1309 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1339 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1342 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1410 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1413 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1417 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1422 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1529 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1535 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1559 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1562 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1577 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1586 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1694 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1725 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
1763 sky2_write32(hw, B0_IMSK, imask);
2046 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2047 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2050 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
2054 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
2057 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2073 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
2076 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2093 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
2094 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
2095 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
2123 sky2_write32(hw, B0_IMSK, 0);
2135 sky2_write32(hw, B0_IMSK, imask);
2346 sky2_write32(hw, B0_IMSK, imask);
2392 sky2_write32(hw, B0_IMSK, 0);
2430 sky2_write32(hw, B0_IMSK, imask);
2680 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2793 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2832 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2838 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2873 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2924 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
3061 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3238 sky2_write32(hw, CPU_WDOG, 0);
3249 sky2_write32(hw, CPU_WDOG, 0);
3269 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3306 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3312 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3346 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3350 sky2_write32(hw, B2_I2C_IRQ, 1);
3357 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3385 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3393 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3394 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3396 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3397 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3411 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3412 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3413 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3416 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3461 sky2_write32(hw, B0_IMSK, 0);
3500 sky2_write32(hw, B0_IMSK, imask);
4109 sky2_write32(hw, STAT_TX_TIMER_INI,
4118 sky2_write32(hw, STAT_LEV_TIMER_INI,
4127 sky2_write32(hw, STAT_ISR_TIMER_INI,
4387 sky2_write32(sky2->hw,
4841 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4860 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4876 sky2_write32(hw, B0_IMSK, 0);
5154 sky2_write32(hw, B0_IMSK, 0);