Lines Matching defs:ctrl
159 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
160 if (ctrl == 0xffff)
163 if (!(ctrl & GM_SMI_CT_BUSY))
185 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
186 if (ctrl == 0xffff)
189 if (ctrl & GM_SMI_CT_RD_VAL) {
328 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
349 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
353 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
366 ctrl &= ~PHY_M_PC_EN_DET_MSK;
369 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
375 ctrl &= ~PHY_M_PC_DSC_MSK;
376 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
383 ctrl &= ~PHY_M_PC_MDIX_MSK;
386 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
394 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
395 ctrl &= ~PHY_M_MAC_MD_MSK;
396 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
397 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
404 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
405 ctrl |= PHY_M_FIB_SIGD_POL;
406 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
412 ctrl = PHY_CT_RESET;
440 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
450 ctrl |= PHY_CT_SP1000;
454 ctrl |= PHY_CT_SP100;
461 ctrl |= PHY_CT_DUP_MD;
488 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
499 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
502 ctrl &= ~PHY_M_FELP_LED1_MSK;
504 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
505 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
510 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
511 ctrl |= PHY_M_PC_ENA_LIP_NP;
514 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
515 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
518 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
522 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
719 u16 ctrl;
731 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
733 ctrl &= ~PHY_M_MAC_GMIF_PUP;
734 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
751 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
753 ctrl |= PHY_M_PC_POW_D_ENA;
754 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
812 u16 ctrl;
825 ctrl = sky2->advertising;
836 sky2->advertising = ctrl;
849 ctrl = 0;
851 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
853 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
856 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
858 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
860 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
861 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
1105 le->ctrl = 0;
1137 le->ctrl = 0;
1271 le->ctrl = 0;
1835 u8 ctrl;
1879 ctrl = 0;
1890 ctrl |= INS_VLAN;
1897 ctrl |= CALSUM; /* auto checksum */
1905 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1907 ctrl |= UDPTCP;
1915 le->ctrl = 1; /* one packet */
1929 le->ctrl = ctrl;
1958 le->ctrl = ctrl;
1963 le->ctrl |= EOP;
2067 u16 ctrl;
2079 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2080 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
2081 gma_write16(hw, port, GM_GP_CTRL, ctrl);
4598 if (le->ctrl & EOP) {