Lines Matching defs:reg
153 /* B0_POWER_CTRL 8 Bit Power Control reg (YUKON only) */
476 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
523 /* PHY addresses (bits 12..8 of PHY address reg) */
528 /* GPHY address (bits 15..11 of SMI control reg) */
2024 XM_PAUSE_DA = 0x0068, /* NA reg r/w Pause Destination Address */
2031 #define XM_EXM(reg) (XM_EXM_START + ((reg) << 3))
2035 XM_SRC_CHK = 0x0100, /* NA reg r/w Source Check Address Register */
2036 XM_SA = 0x0108, /* NA reg r/w Station Address Register */
2043 XM_LSA = 0x0128, /* NA reg r/o Last Source Register */
2476 static inline u32 skge_read32(const struct skge_hw *hw, int reg)
2478 return readl(hw->regs + reg);
2481 static inline u16 skge_read16(const struct skge_hw *hw, int reg)
2483 return readw(hw->regs + reg);
2486 static inline u8 skge_read8(const struct skge_hw *hw, int reg)
2488 return readb(hw->regs + reg);
2491 static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val)
2493 writel(val, hw->regs + reg);
2496 static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val)
2498 writew(val, hw->regs + reg);
2501 static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
2503 writeb(val, hw->regs + reg);
2507 #define SK_REG(port,reg) (((port)<<7)+(u16)(reg))
2508 #define SK_XMAC_REG(port, reg) \
2509 ((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2511 static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg)
2514 v = skge_read16(hw, SK_XMAC_REG(port, reg));
2515 v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16;
2519 static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg)
2521 return skge_read16(hw, SK_XMAC_REG(port,reg));
2535 static inline void xm_outhash(const struct skge_hw *hw, int port, int reg,
2538 xm_write16(hw, port, reg, (u16)hash[0] | ((u16)hash[1] << 8));
2539 xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8));
2540 xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8));
2541 xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8));
2544 static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg,
2547 xm_write16(hw, port, reg, (u16)addr[0] | ((u16)addr[1] << 8));
2548 xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8));
2549 xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8));
2552 #define SK_GMAC_REG(port,reg) \
2553 (BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2555 static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg)
2557 return skge_read16(hw, SK_GMAC_REG(port,reg));
2560 static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg)
2562 return (u32) skge_read16(hw, SK_GMAC_REG(port,reg))
2563 | ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16);
2571 static inline void gma_set_addr(struct skge_hw *hw, int port, int reg,
2574 gma_write16(hw, port, reg, (u16) addr[0] | ((u16) addr[1] << 8));
2575 gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
2576 gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));