Lines Matching refs:skge_write32
180 skge_write32(hw, B2_GP_IO, reg);
183 skge_write32(hw, SK_REG(port, GPHY_CTRL),
188 skge_write32(hw, SK_REG(port, GPHY_CTRL),
193 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
670 skge_write32(hw, B2_IRQM_MSK, msk);
672 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
674 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
675 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
693 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
697 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
712 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
719 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
1141 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1562 skge_write32(hw, B2_GP_IO, r);
1720 skge_write32(hw, B2_GP_IO, reg);
2053 skge_write32(hw, B2_FAR, reg);
2069 skge_write32(hw, B2_GP_IO, reg);
2073 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2074 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2082 skge_write32(hw, B2_GP_IO, reg);
2091 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2092 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2093 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2121 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2488 skge_write32(hw, RB_ADDR(q, RB_START), start);
2489 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2490 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2491 skge_write32(hw, RB_ADDR(q, RB_END), end);
2495 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2497 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2521 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2522 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2523 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2524 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2613 skge_write32(hw, B0_IMSK, hw->intr_mask);
2640 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2642 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2666 skge_write32(hw, B0_IMSK, (hw->ports == 1) ? 0 : hw->intr_mask);
2681 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2690 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2691 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2694 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2695 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
3229 skge_write32(hw, B0_IMSK, hw->intr_mask);
3301 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3307 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3363 skge_write32(hw, B0_IMSK, hw->intr_mask);
3428 skge_write32(hw, B0_IMSK, hw->intr_mask);
3658 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3663 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3664 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3665 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3668 skge_write32(hw, B0_IMSK, 0);
4034 skge_write32(hw, B0_IMSK, 0);
4074 skge_write32(hw, B0_IMSK, 0);